UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 13: LPC2300 USB device
Table 270. USB Command Code register (USBCmdCode - address 0xFFE0 C210) bit description
Bit Symbol Value Description Reset value
7:0 - - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
15:8 CMD_PHASE The command phase: 0x00
23:16 CMD_CODE/
CMD_WDATA
0x01
0x02
0x05
Read
Write
Command
This is a multi-purpose field. When CMD_PHASE is
Command or Read, this field contains the code for the
command (CMD_CODE). When CMD_PHASE is Write,
this field contains the command write data
(CMD_WDATA).
31:24 - - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
0x00
NA
8.7.2 USB Command Data register (USBCmdData - 0xFFE0 C214)
This register contains the data retrieved after executing a SIE command. When the data is
ready to be read, the CD_FULL bit of the USBDevIntSt register is set. See Table 13–242
for details. USBCmdData is a read only register.
Table 271. USB Command Data register (USBCmdData - address 0xFFE0 C214) bit
description
Bit Symbol Description Reset value
7:0 CMD_RDATA Command Read Data. 0x00
31:8 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
8.8 DMA registers
The registers in this group are used for the DMA mode of operation (see Section 13–13
“DMA operation”)
8.8.1 USB DMA Request Status register (USBDMARSt - 0xFFE0 C250)
A bit in this register associated with a non-isochronous endpoint is set by hardware when
an endpoint interrupt occurs (see the description of USBEpIntSt) and the corresponding
bit in USBEpIntEn is 0. A bit associated with an isochronous endpoint is set when the
corresponding bit in USBEpIntEn is 0 and a FRAME interrupt occurs. A set bit serves as
a flag for the DMA engine to start the data transfer if the DMA is enabled for the
corresponding endpoint in the USBEpDMASt register. The DMA cannot be enabled for
control endpoints (EP0 and EP1). USBDMARSt is a read only register.
Table 272. USB DMA Request Status register (USBDMARSt - address 0xFFE0 C250) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol EP31 EP30 EP29 EP28 EP27 EP26 EP25 EP24
Bit 23 22 21 20 19 18 17 16
Symbol EP23 EP22 EP21 EP20 EP19 EP18 EP17 EP16
UM10211_1
© NXP B.V. 2007. All rights reserved.
User manual Rev. 01 — 27 March 2007 286 of 613