UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 11: LPC2300 Ethernet
connection to the PHY chip: 2.5 MHz at 10 Mbps or 25 MHz at 100 Mbps. The RMII
interface allows a low pin count double clock data connection to the PHY. Registers in the
PHY chip are accessed via the AHB interface through the serial management connection
of the MII bus (MIIM) operating at 2.5 MHz.
7.2 Example PHY Devices
Some examples of compatible PHY devices are shown in Table 11–130.
Table 130. Example PHY Devices
Manufacturer
Broadcom
ICS
Intel
LSI Logic
Micrel
National
SMSC
Part Number(s)
BCM5221
ICS1893
LXT971A
L80223, L80225, L80227
KS8721
DP83847, DP83846, DP83843
LAN83C185
8. Pin description
Table 11–131 shows the signals used for the Reduced Media Independent Interface
(RMII) to the external PHY.
Table 131. Ethernet RMII pin descriptions
Pin Name Type Pin Description
ENET_TX_EN Output Transmit data enable
ENET_TXD[1:0] Output Transmit data, 2 bits
ENET_RXD[1:0] Input Receive data, 2 bits.
ENET_RX_ER Input Receive error.
ENET_CRS Input Carrier sense/data valid.
ENET_REF_CLK Input Reference clock
Table 11–132 shows the signals used for Media Independent Interface Management
(MIIM) of the external PHY.
Table 132. Ethernet MIIM pin descriptions
Pin Name Type Pin Description
ENET_MDC Output MIIM clock.
ENET_MDIO Input/Output MI data input and output
9. Registers and software interface
The software interface of the Ethernet block consists of a register view and the format
definitions for the transmit and receive descriptors. These two aspects are addressed in
the next two subsections.
UM10211_1
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User manual Rev. 01 — 27 March 2007 139 of 613