UM10211 - Standard ICs

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NXP Semiconductors UM10211 Chapter 1: Introductory information 9. Block diagram XTAL1 TMS TDI trace signals XTAL2 V DDA TRST TCK TDO RESET V DD(3V3) EXTIN0 P0, P1, P2, P3, P4 LPC2364/66/68 HIGH-SPEED GPI/O 70 PINS TOTAL 8/32 kB SRAM 128/256/ 512 kB FLASH INTERNAL CONTROLLERS SRAM FLASH TEST/DEBUG INTERFACE ARM7TDMI-S EMULATION TRACE MODULE PLL system clock VECTORED INTERRUPT CONTROLLER SYSTEM FUNCTIONS INTERNAL RC OSCILLATOR VREF V SSA , V SS V DD(DCDC)(3V3) AHB2 AHB BRIDGE AHB BRIDGE AHB1 RMII(8) ETHERNET MAC WITH DMA 16 kB SRAM MASTER PORT AHB TO APB BRIDGE AHB TO APB BRIDGE SLAVE PORT 8 kB SRAM USB WITH 4 kB RAM AND DMA GP DMA CONTROLLER V BUS USB_D+, USB_D− USB_CONNECT USB_UP_LED EINT3 to EINT0 P0, P2 2 × CAP0/CAP1/ CAP2/CAP3 4 × MAT2, 2 × MAT0/MAT1/ MAT3 6 × PWM1 2 × PCAP1 EXTERNAL INTERRUPTS CAPTURE/COMPARE TIMER0/TIMER1/ TIMER2/TIMER3 PWM1 I 2 S INTERFACE SPI, SSP0 INTERFACE I2SRX_CLK I2STX_CLK I2SRX_WS I2STX_WS I2SRX_SDA I2STX_SDA SCK, SCK0 MOSI, MOSI0 MISO, MISO0 SSEL, SSEL1 P0, P1 LEGACY GPI/O 52 PINS TOTAL SSP1 INTERFACE SCK1 MOSI1 MIS01 SSEL1 6 × AD0 AOUT VBAT power domain 2 RTCX1 RTCX2 A/D CONVERTER D/A CONVERTER 2 kB BATTERY RAM RTC OSCILLATOR REAL- TIME CLOCK SD/MMC CARD INTERFACE (1) UART0, UART2, UART3 UART1 MCICLK, MCIPWR MCICMD, MCIDAT[3:0] TXD0, TXD2, TXD3 RXD0, RXD2, RXD3 TXD1 RXD1 DTR1, RTS1 DSR1, CTS1, DCD1, RI1 WATCHDOG TIMER CAN1, CAN2 RD1, RD2 TD1, TD2 SYSTEM CONTROL I 2 C0, I 2 C1, I 2 C2 SCL0, SCL1, SCL2 SDA0, SDA1, SDA2 002aac566 Fig 1. (1) LPC2368 only. LPC2364/6/8 block diagram UM10211_1 © NXP B.V. 2007. All rights reserved. User manual Rev. 01 — 27 March 2007 8 of 613
NXP Semiconductors UM10211 Chapter 1: Introductory information TMS TRST TCK TDI trace signals TDO EXTIN0 DBGEN XTAL1 XTAL2 V DD(3V3) RESET V DDA P0, P1, P2, P3, P4 LPC2378 HIGH-SPEED GPI/O 104 PINS TOTAL 32 kB SRAM 512 kB FLASH INTERNAL CONTROLLERS SRAM FLASH TEST/DEBUG INTERFACE ARM7TDMI-S EMULATION TRACE MODULE PLL system clock VECTORED INTERRUPT CONTROLLER SYSTEM FUNCTIONS INTERNAL RC OSCILLATOR EXTERNAL MEMORY CONTROLLER VREF V SSA , V SS V DD(DCDC)(3V3) D[7:0] A[15:0] WE, OE, CS0, CS1 AHB2 AHB BRIDGE AHB BRIDGE AHB1 RMII(8) ETHERNET MAC WITH DMA 16 kB SRAM MASTER PORT AHB TO APB BRIDGE AHB TO APB BRIDGE SLAVE PORT 8 kB SRAM USB WITH 4 kB RAM AND DMA GP DMA CONTROLLER V BUS 2 × USB_D+/USB_D− 2 × USB_CONNECT 2 × USB_UP_LED EINT3 to EINT0 P0, P2 2 × CAP0/CAP1/ CAP2/CAP3 4 × MAT2, 2 × MAT0/MAT1/ MAT3 6 × PWM1 2 × PCAP1 EXTERNAL INTERRUPTS CAPTURE/COMPARE TIMER0/TIMER1/ TIMER2/TIMER3 PWM1 I 2 S INTERFACE SPI, SSP0 INTERFACE I2SRX_CLK I2STX_CLK I2SRX_WS I2STX_WS I2SRX_SDA I2STX_SDA SCK, SCK0 MOSI, MOSI0 MISO, MISO0 SSEL, SSEL1 P0, P1 LEGACY GPI/O 56 PINS TOTAL SSP1 INTERFACE SCK1 MOSI1 MIS01 SSEL1 8 × AD0 AOUT VBAT power domain 2 RTCX1 RTCX2 ALARM A/D CONVERTER D/A CONVERTER 2 kB BATTERY RAM RTC OSCILLATOR REAL- TIME CLOCK WATCHDOG TIMER SYSTEM CONTROL SD/MMC CARD INTERFACE UART0, UART2, UART3 UART1 CAN1, CAN2 I 2 C0, I 2 C1, I 2 C2 MCICLK, MCIPWR MCICMD, MCIDAT[3:0] TXD0, TXD2, TXD3 RXD0, RXD2, RXD3 TXD1 RXD1 DTR1, RTS1 DSR1, CTS1, DCD1, RI1 RD1, RD2 TD1, TD2 SCL0, SCL1, SCL2 SDA0, SDA1, SDA2 002aac574 Fig 2. LPC2378 block diagram UM10211_1 © NXP B.V. 2007. All rights reserved. User manual Rev. 01 — 27 March 2007 9 of 613
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UM10211 - Standard ICs

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