UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 32: Supplementary information
address 0xE001 0030) bit description . . . . . .362
Table 341.SPI Data To Clock Phase Relationship. . . . . .366
Table 342.SPI Pin Description. . . . . . . . . . . . . . . . . . . . .370
Table 343.SPI Register Map . . . . . . . . . . . . . . . . . . . . . .370
Table 344:SPI Control Register (S0SPCR - address
0xE002 0000) bit description . . . . . . . . . . . . .371
Table 345:SPI Status Register (S0SPSR - address
0xE002 0004) bit description . . . . . . . . . . . . .372
Table 346:SPI Data Register (S0SPDR - address
0xE002 0008) bit description . . . . . . . . . . . . .373
Table 347:SPI Clock Counter Register (S0SPCCR - address
0xE002 000C) bit description . . . . . . . . . . . . .373
Table 348:SPI Test Control Register (SPTCR - address
0xE002 0010) bit description . . . . . . . . . . . . .373
Table 349:SPI Test Status Register (SPTSR - address
0xE002 0014) bit description . . . . . . . . . . . . .374
Table 350:SPI Interrupt Register (S0SPINT - address
0xE002 001C) bit description . . . . . . . . . . . . .374
Table 351.SSP pin descriptions . . . . . . . . . . . . . . . . . . .377
Table 352.SSP Register Map . . . . . . . . . . . . . . . . . . . . .385
Table 353:SSPn Control Register 0 (SSP0CR0 - address
0xE006 8000, SSP1CR0 - 0xE003 0000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .386
Table 354:SSPn Control Register 1 (SSP0CR1 - address
0xE006 8004, SSP1CR1 - 0xE003 0004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .387
Table 355:SSPn Data Register (SSP0DR - address
0xE006 8008, SSP1DR - 0xE003 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .387
Table 356:SSPn Status Register (SSP0SR - address
0xE006 800C, SSP1SR - 0xE003 000C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .388
Table 357:SSPn Clock Prescale Register (SSP0CPSR -
address 0xE006 8010, SSP1CPSR -
0xE003 8010) bit description . . . . . . . . . . . . .388
Table 358:SSPn Interrupt Mask Set/Clear register
(SSP0IMSC - address 0xE006 8014, SSP1IMSC
- 0xE003 0014) bit description . . . . . . . . . . . .389
Table 359:SSPn Raw Interrupt Status register (SSP0RIS -
address 0xE006 8018, SSP1RIS - 0xE003 0018)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .389
Table 360:SSPn Masked Interrupt Status register (SSPnMIS
-address 0xE006 801C, SSP1MIS -
0xE003 001C) bit description . . . . . . . . . . . . .390
Table 361:SSPn interrupt Clear Register (SSP0ICR -
address 0xE006 8020, SSP1ICR - 0xE003 0020)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .390
Table 362:SSPn DMA Control Register (SSP0DMACR -
address 0xE006 8024, SSP1DMACR -
0xE003 0024) bit description . . . . . . . . . . . . .390
Table 363.SD/MMC card interface pin description . . . . .391
Table 364.Command format . . . . . . . . . . . . . . . . . . . . . . 395
Table 365.Simple response format . . . . . . . . . . . . . . . . . 396
Table 366.Long response format . . . . . . . . . . . . . . . . . . 396
Table 367.Command path status flags . . . . . . . . . . . . . . 396
Table 368.CRC token status. . . . . . . . . . . . . . . . . . . . . . 400
Table 369.Data path status flags . . . . . . . . . . . . . . . . . . 400
Table 370.Transmit FIFO status flags. . . . . . . . . . . . . . . 401
Table 371.Receive FIFO status flags . . . . . . . . . . . . . . . 402
Table 372.SPI register map . . . . . . . . . . . . . . . . . . . . . . 402
Table 373:Power Control register (MCIPower - address
0xE008 C000) bit description. . . . . . . . . . . . . 403
Table 374:Clock Control register (MCIClock - address
0xE008 C004) bit description. . . . . . . . . . . . . 404
Table 375:Argument register (MCIArgument - address
0xE008 C008) bit description. . . . . . . . . . . . . 404
Table 376:Command register (MCICommand - address
0xE008 C00C) bit description . . . . . . . . . . . . 405
Table 377:Command Response Types. . . . . . . . . . . . . . 405
Table 378:Command Response register
(MCIRespCommand - address 0xE008 C010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Table 379:Response registers (MCIResponse0-3 -
addresses 0xE008 0014, 0xE008 C018,
0xE008 001C and 0xE008 C020) bit description .
406
Table 380:Response Register Type . . . . . . . . . . . . . . . . 406
Table 381:Data Timer register (MCIDataTimer - address
0xE008 C024) bit description. . . . . . . . . . . . . 406
Table 382:Data Length register (MCIDataLength - address
0xE008 C028) bit description. . . . . . . . . . . . . 406
Table 383:Data Control register (MCIDataCtrl - address
0xE008 C02C) bit description . . . . . . . . . . . . 407
Table 384:Data Block Length . . . . . . . . . . . . . . . . . . . . . 407
Table 385:Data Counter register (MCIDataCnt - address
0xE008 C030) bit description. . . . . . . . . . . . . 408
Table 386:Status register (MCIStatus - address
0xE008 C034) bit description. . . . . . . . . . . . . 408
Table 387:Clear register (MCIClear - address 0xE008 C038)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 409
Table 388:Interrupt Mask registers (MCIMask0 - address
0xE008 C03C and MCIMask1 - address
0xE008 C040) bit description. . . . . . . . . . . . . 409
Table 389:FIFO Counter register (MCIFifoCnt - address
0xE008 C048) bit description. . . . . . . . . . . . . 410
Table 390:Data FIFO register (MCIFIFO - address
0xE008 C080 to 0xE008 C0BC) bit description . .
411
Table 391.I 2 C Pin Description. . . . . . . . . . . . . . . . . . . . . 413
Table 392.I2CnCONSET used to configure Master mode . .
414
Table 393.I2CnCONSET used to configure Slave mode 415
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UM10211_1
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User manual Rev. 01 — 27 March 2007 591 of 613