UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 11: LPC2300 Ethernet
Two registers, TxConsumeIndex and TxProduceIndex, define the descriptor locations that
will be used next by hardware and software. Both register act as counters starting at 0 and
wrapping when they reach the value of TxDescriptorNumber. The TxProduceIndex
contains the index of the next descriptor that is going to be filled by the software driver.
The TxConsumeIndex contains the index of the next descriptor going to be transmitted by
the hardware. When TxProduceIndex == TxConsumeIndex, the transmit buffer is empty.
When TxProduceIndex == TxConsumeIndex -1 (taking wraparound into account), the
transmit buffer is full and the software driver cannot add new descriptors until the
hardware has transmitted one or more frames to free up descriptors.
Each transmit descriptor takes two word locations (8 bytes) in memory. Likewise each
status field takes one word (4 bytes) in memory. Each transmit descriptor consists of a
pointer to the data buffer containing transmit data (Packet) and a control word (Control).
The Packet field has a zero address offset, whereas the control field has a 4 byte address
offset, see Table 11–185.
Table 185. Transmit descriptor fields
Symbol Address offset Bytes Description
Packet 0x0 4 Base address of the data buffer containing transmit data.
Control 0x4 4 Control information, see Table 11–186.
The data buffer pointer (Packet) is a 32 bit, byte aligned address value containing the
base address of the data buffer. The definition of the control word bits is listed in
Table 11–186.
Table 186. Transmit descriptor control word
Bit Symbol Description
10:0 Size Size in bytes of the data buffer. This is the size of the frame or fragment as it
needs to be fetched by the DMA manager. In most cases it will be equal to the
byte size of the data buffer pointed to by the Packet field of the descriptor. Size
is -1 encoded e.g. a buffer of 8 bytes is encoded as the Size value 7.
25:11 - Unused
26 Override Per frame override. If true, bits 30:27 will override the defaults from the MAC
internal registers. If false, bits 30:27 will be ignored and the default values
from the MAC will be used.
27 Huge If true, enables huge frame, allowing unlimited frame sizes. When false,
prevents transmission of more than the maximum frame length (MAXF[15:0]).
28 Pad If true, pad short frames to 64 bytes.
29 CRC If true, append a hardware CRC to the frame.
30 Last If true, indicates that this is the descriptor for the last fragment in the transmit
frame. If false, the fragment from the next descriptor should be appended.
31 Interrupt If true, a TxDone interrupt will be generated when the data in this frame or
frame fragment has been sent and the associated status information has been
committed to memory.
Table 11–187 shows the one field transmit status.
Table 187. Transmit status fields
Symbol Address Bytes Description
offset
StatusInfo 0x0 4 Transmit status return flags, see Table 11–188.
UM10211_1
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User manual Rev. 01 — 27 March 2007 168 of 613