UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 18: LPC2300 SD_MMC
UM10211_1
The receive FIFO is accessible via 16 sequential addresses (see Section 18–5.16 “Data
FIFO Register (MCIFIFO - 0xE008 C080 to 0xE008 C0BC)”).
If the receive FIFO is disabled, all status flags are deasserted, and the read and write
pointers are reset. The data path subunit asserts RxActive when it receives data.
Table 18–371 lists the receive FIFO status flags.
4.3.16 APB interfaces
The APB interface generates the interrupt and DMA requests, and accesses the MCI
adapter registers and the data FIFO. It consists of a data path, register decoder, and
interrupt/DMA logic. DMA is controlled by the General Purpose DMA controller, see that
chapter for details.
4.3.17 Interrupt logic
5. Register description
Table 371. Receive FIFO status flags
Symbol
RxFifoFull
RxFifoEmpty
RxHalfFull
RxDataAvlbl
RxOverrun
The interrupt logic generates an interrupt request signal that is asserted when at least one
of the selected status flags is HIGH. A mask register is provided to allow selection of the
conditions that will generate an interrupt. A status flag generates the interrupt request if a
corresponding mask flag is set.
This section describes the MCI registers and provides programming details.
5.1 Summary of MCI Registers
Description
Set to HIGH when all 16 receive FIFO words contain valid data.
Set to HIGH when the receive FIFO does not contain valid data.
Set to HIGH when 8 or more receive FIFO words contain valid data. This
flag can be used as a DMA request.
Set to HIGH when the receive FIFO is not empty. This flag is the inverse
of the RxFifoEmpty flag.
Set to HIGH when an overrun error occurs. This flag is cleared by writing
to the MCIClear register.
The MCI registers are shown in Table 18–372.
Table 372. SPI register map
Name Description Access Width Reset Address
Value [1]
MCIPower Power control register. R/W 8 0x00 0xE008 C000
MCIClock Clock control register. R/W 12 0x000 0xE008 C004
MCIArgument Argument register. R/W 32 0x00000000 0xE008 C008
MMCCommand Command register. R/W 11 0x000 0xE008 C00C
MCIRespCmd Response command register. RO 6 0x00 0xE008 C010
MCIResponse0 Response register. RO 32 0x00000000 0xE008 C014
MCIResponse1 Response register. RO 32 0x00000000 0xE008 C018
MCIResponse2 Response register. RO 32 0x00000000 0xE008 C01C
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User manual Rev. 01 — 27 March 2007 402 of 613