UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 26: LPC2300 RTC
3. Architecture
CLOCK GENERATOR
CLK32k
MUX
RTC OSCILLATOR
REFERENCE CLOCK DIVIDER
(PRESCALER)
CLK1
CCLK
strobe
TIME COUNTERS
COMPARATORS
ALARM
REGISTERS
counter
enables
COUNTER INCREMENT
INTERRUPT ENABLE
ALARM MASK
REGISTER
INTERRUPT GENERATOR
Fig 102.RTC block diagram
4. Register description
The RTC includes a number of registers. The address space is split into four sections by
functionality. The first eight addresses are the Miscellaneous Register Group
(Section 26–4.2). The second set of eight locations are the Time Counter Group
(Section 26–4.4). The third set of eight locations contain the Alarm Register Group
(Section 26–5). The remaining registers control the Reference Clock Divider.
The Real Time Clock includes the register shown in Table 26–463. Detailed descriptions
of the registers follow. In these descriptions, for most of the registers the Reset Value
column shows "NC", meaning that these registers are not changed by a Reset. Software
must initialize these registers between power-on and setting the RTC into operation.
Table 463. Real Time Clock register map
Name Size Description Access Reset Address
Value [1]
ILR 2 Interrupt Location Register R/W * 0xE002 4000
CTC 15 Clock Tick Counter RO * 0xE002 4004
CCR 4 Clock Control Register R/W * 0xE002 4008
CIIR 8 Counter Increment Interrupt Register R/W * 0xE002 400C
AMR 8 Alarm Mask Register R/W * 0xE002 4010
CTIME0 32 Consolidated Time Register 0 RO * 0xE002 4014
CTIME1 32 Consolidated Time Register 1 RO * 0xE002 4018
UM10211_1
© NXP B.V. 2007. All rights reserved.
User manual Rev. 01 — 27 March 2007 500 of 613