UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 13: LPC2300 USB device
8.3.6 USB Device Interrupt Priority register (USBDevIntPri - 0xFFE0 C22C)
Writing one to a bit in this register causes the corresponding interrupt to be routed to the
USB_INT_REQ_HP interrupt line. Writing zero causes the interrupt to be routed to the
USB_INT_REQ_LP interrupt line. Either the EP_FAST or FRAME interrupt can be routed
to USB_INT_REQ_HP, but not both. If the software attempts to set both bits to one, no
interrupt will be routed to USB_INT_REQ_HP. USBDevIntPri is a write only register.
Table 250. USB Device Interrupt Priority register (USBDevIntPri - address 0xFFE0 C22C) bit description
Bit Symbol Value Description Reset value
0 FRAME 0 FRAME interrupt is routed to USB_INT_REQ_LP. 0
1 FRAME interrupt is routed to USB_INT_REQ_HP.
1 EP_FAST 0 EP_FAST interrupt is routed to USB_INT_REQ_LP. 0
1 EP_FAST interrupt is routed to USB_INT_REQ_HP.
7:2 - - Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
NA
8.4 Endpoint interrupt registers
The registers in this group facilitate handling of endpoint interrupts. Endpoint interrupts are
used in Slave mode operation.
8.4.1 USB Endpoint Interrupt Status register (USBEpIntSt - 0xFFE0 C230)
Each physical non-isochronous endpoint is represented by a bit in this register to indicate
that it has generated an interrupt. All non-isochronous OUT endpoints generate an
interrupt when they receive a packet without an error. All non-isochronous IN endpoints
generate an interrupt when a packet is successfully transmitted, or when a NAK
handshake is sent on the bus and the interrupt on NAK feature is enabled (see Section
13–10.3 “Set Mode (Command: 0xF3, Data: write 1 byte)” on page 298). A bit set to one in
this register causes either the EP_FAST or EP_SLOW bit of USBDevIntSt to be set
depending on the value of the coreesponding bit of USBEpDevIntPri. USBEpIntSt is a
read only register.
Note that for Isochronous endpoints, handling of packet data is done when the FRAME
interrupt occurs.
Table 251. USB Endpoint Interrupt Status register (USBEpIntSt - address 0xFFE0 C230) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX EP12RX
Bit 23 22 21 20 19 18 17 16
Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX EP8RX
Bit 15 14 13 12 11 10 9 8
Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX
Bit 7 6 5 4 3 2 1 0
Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX
UM10211_1
© NXP B.V. 2007. All rights reserved.
User manual Rev. 01 — 27 March 2007 276 of 613