UM10211 - Standard ICs

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NXP Semiconductors UM10211 Chapter 11: LPC2300 Ethernet 4. DMA engine functions – The receive filter which can filter out certain Ethernet frames by applying different filtering schemes. – The receive buffer implementing a delay for receive frames to allow the filter to filter out certain frames before storing them to memory. The Ethernet block is designed to provide optimized performance via DMA hardware acceleration. Independent scatter/gather DMA engines connected to the AHB bus off-load many data transfers from the ARM7 CPU. Descriptors, which are stored in memory, contain information about fragments of incoming or outgoing Ethernet frames. A fragment may be an entire frame or a much smaller amount of data. Each descriptor contains a pointer to a memory buffer that holds data associated with a fragment, the size of the fragment buffer, and details of how the fragment will be transmitted or received. Descriptors are stored in arrays in memory, which are located by pointer registers in the Ethernet block. Other registers determine the size of the arrays, point to the next descriptor in each array that will be used by the DMA engine, and point to the next descriptor in each array that will be used by the Ethernet device driver. 5. Overview of DMA operation The DMA engine makes use of a Receive descriptor array and a Transmit descriptor array in memory. All or part of an Ethernet frame may be contained in a memory buffer associated with a descriptor. When transmitting, the transmit DMA engine uses as many descriptors as needed (one or more) to obtain (gather) all of the parts of a frame, and sends them out in sequence. When receiving, the receive DMA engine also uses as many descriptors as needed (one or more) to find places to store (scatter) all of the data in the received frame. The base address registers for the descriptor array, registers indicating the number of descriptor array entries, and descriptor array input/output pointers are contained in the Ethernet block. The descriptor entries and all transmit and receive packet data are stored in memory which is not a part of the Ethernet block. The descriptor entries tell where related frame data is stored in memory, certain aspects of how the data is handled, and the result status of each Ethernet transaction. Hardware in the DMA engine controls how data incoming from the Ethernet MAC is saved to memory, causes fragment related status to be saved, and advances the hardware receive pointer for incoming data. Driver software must handle the disposition of received data, changing of descriptor data addresses (to avoid unnecessary data movement), and advancing the software receive pointer. The two pointers create a circular queue in the descriptor array and allow both the DMA hardware and the driver software to know which descriptors (if any) are available for their use, including whether the descriptor array is empty or full. UM10211_1 © NXP B.V. 2007. All rights reserved. User manual Rev. 01 — 27 March 2007 136 of 613
NXP Semiconductors UM10211 Chapter 11: LPC2300 Ethernet 6. Ethernet Packet Similarly, driver software must set up pointers to data that will be transmitted by the Ethernet MAC, giving instructions for each fragment of data, and advancing the software transmit pointer for outgoing data. Hardware in the DMA engine reads this information and sends the data to the Ethernet MAC interface when possible, updating the status and advancing the hardware transmit pointer. Figure 11–19 illustrates the different fields in an Ethernet packet. ethernet packet PREAMBLE 7 bytes ETHERNET FRAME start-of-frame delimiter 1 byte DESTINATION ADDRESS SOURCE ADDRESS OPTIONAL VLAN LEN TYPE PAYLOAD FCS DesA oct6 DesA oct5 DesA oct4 DesA oct3 DesA oct2 DesA oct1 SrcA oct6 SrcA oct5 SrcA oct4 SrcA oct3 SrcA oct2 SrcA oct1 LSB oct(0) oct(1) oct(2) oct(3) oct(4) oct(5) oct(6) MSB oct(7) time Fig 19. Ethernet packet fields A packet consists of a preamble, a start-of-frame delimiter and an Ethernet frame. The Ethernet frame consists of the destination address, the source address, an optional VLAN field, the length/type field, the payload and the frame check sequence. Each address consists of 6 bytes where each byte consists of 8 bits. Bits are transferred starting with the least significant bit. UM10211_1 © NXP B.V. 2007. All rights reserved. User manual Rev. 01 — 27 March 2007 137 of 613
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UM10211 Chapter 16: SPI interface S
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UM10211 - Standard ICs

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