UM10211 - Standard ICs

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NXP Semiconductors UM10211 Chapter 13: LPC2300 USB device Table 280. USB DMA Interrupt Status register (USBDMAIntSt - address 0xFFE0 C290) bit description Bit Symbol Value Description Reset value 0 EOT End of Transfer Interrupt bit. 0 0 All bits in the USBEoTIntSt register are 0. 1 At least one bit in the USBEoTIntSt is set. 1 NDDR New DD Request Interrupt bit. 0 0 All bits in the USBNDDRIntSt register are 0. 1 At least one bit in the USBNDDRIntSt is set. 2 ERR System Error Interrupt bit. 0 0 All bits in the USBSysErrIntSt register are 0. 1 At least one bit in the USBSysErrIntSt is set. 31:3 - - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 8.8.9 USB DMA Interrupt Enable register (USBDMAIntEn - 0xFFE0 C294) Writing a one to a bit in this register enables the corresponding bit in USBDMAIntSt to generate an interrupt on the USB_INT_REQ_DMA interrupt line when set. USBDMAIntEn is a read/write register. Table 281. USB DMA Interrupt Enable register (USBDMAIntEn - address 0xFFE0 C294) bit description Bit Symbol Valu e Description 0 EOT End of Transfer Interrupt enable bit. 0 0 The End of Transfer Interrupt is disabled. 1 The End of Transfer Interrupt is enabled. 1 NDDR New DD Request Interrupt enable bit. 0 0 The New DD Request Interrupt is disabled. 1 The New DD Request Interrupt is enabled. 2 ERR System Error Interrupt enable bit. 0 0 The System Error Interrupt is disabled. 1 The System Error Interrupt is enabled. 31:3 - - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Reset value 8.8.10 USB End of Transfer Interrupt Status register (USBEoTIntSt - 0xFFE0 C2A0) When the DMA transfer completes for the current DMA descriptor, either normally (descriptor is retired) or because of an error, the bit corresponding to the endpoint is set in this register. The cause of the interrupt is recorded in the DD_status field of the descriptor. USBEoTIntSt is a read only register. UM10211_1 © NXP B.V. 2007. All rights reserved. User manual Rev. 01 — 27 March 2007 290 of 613
NXP Semiconductors UM10211 Chapter 13: LPC2300 USB device Table 282. USB End of Transfer Interrupt Status register (USBEoTIntSt - address 0xFFE0 C2A0s) bit description Bit Symbol Value Description Reset value 31:0 EPxx Endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 0 0 There is no End of Transfer interrupt request for endpoint xx. 1 There is an End of Transfer Interrupt request for endpoint xx. 8.8.11 USB End of Transfer Interrupt Clear register (USBEoTIntClr - 0xFFE0 C2A4) Writing one to a bit in this register clears the corresponding bit in the USBEoTIntSt register. Writing zero has no effect. USBEoTIntClr is a write only register. Table 283. USB End of Transfer Interrupt Clear register (USBEoTIntClr - address 0xFFE0 C2A4) bit description Bit Symbol Value Description Reset value 31:0 EPxx Clear endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 0 0 No effect. 1 Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. 8.8.12 USB End of Transfer Interrupt Set register (USBEoTIntSet - 0xFFE0 C2A8) Writing one to a bit in this register sets the corresponding bit in the USBEoTIntSt register. Writing zero has no effect. USBEoTIntSet is a write only register. Table 284. USB End of Transfer Interrupt Set register (USBEoTIntSet - address 0xFFE0 C2A8) bit description Bit Symbol Value Description Reset value 31:0 EPxx Set endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 0 0 No effect. 1 Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. 8.8.13 USB New DD Request Interrupt Status register (USBNDDRIntSt - 0xFFE0 C2AC) A bit in this register is set when a transfer is requested from the USB device and no valid DD is detected for the corresponding endpoint. USBNDDRIntSt is a read only register. Table 285. USB New DD Request Interrupt Status register (USBNDDRIntSt - address 0xFFE0 C2AC) bit description Bit Symbol Value Description Reset value 31:0 EPxx Endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request. 0 0 There is no new DD interrupt request for endpoint xx. 1 There is a new DD interrupt request for endpoint xx. UM10211_1 © NXP B.V. 2007. All rights reserved. User manual Rev. 01 — 27 March 2007 291 of 613
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UM10211 - Standard ICs

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