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UM10211 - Standard ICs

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NXP Semiconductors<br />

<strong>UM10211</strong><br />

Chapter 3: LPC2300 System control<br />

Table 19.<br />

AHB configuration register map<br />

Name Description Access Reset Address<br />

value<br />

AHBCFG1 Configures the AHB1 arbiter. R/W 0 0xE01F C188<br />

AHBCFG2 Configures the AHB2 arbiter. R/W 0 0xE01F C18C<br />

9.1 AHB Arbiter Configuration register 1 (AHBCFG1 - 0xE01F C188)<br />

Table 20. AHB Arbiter Configuration register 1 (AHBCFG1 - address 0xE01F C188) bit<br />

description<br />

Bit Symbol Value Description Reset<br />

value<br />

0 scheduler 0 Priority scheduling. 0<br />

1 Uniform (round-robin) scheduling.<br />

2:1 break_burst 00 Break all defined length bursts (the CPU does not create 00<br />

defined bursts).<br />

01 Break all defined length bursts greater than four-beat.<br />

10 Break all defined length bursts greater than eight-beat.<br />

11 Never break defined length bursts.<br />

3 quantum_type 0 A quantum is an AHB clock. 1<br />

1 A quantum is an AHB bus cycle.<br />

7:4 quantum_size Controls the type of arbitration and the number of quanta<br />

before re-arbitration occurs.<br />

0000 Preemptive, re-arbitrate after 1 AHB quantum.<br />

0001 Preemptive, re-arbitrate after 2 AHB quanta.<br />

0010 Preemptive, re-arbitrate after 4 AHB quanta.<br />

0011 Preemptive, re-arbitrate after 8 AHB quanta.<br />

0100 Preemptive, re-arbitrate after 16 AHB quanta.<br />

0101 Preemptive, re-arbitrate after 32 AHB quanta.<br />

0110 Preemptive, re-arbitrate after 64 AHB quanta.<br />

0111 Preemptive, re-arbitrate after 128 AHB quanta.<br />

1000 Preemptive, re-arbitrate after 256 AHB quanta.<br />

1001 Preemptive, re-arbitrate after 512 AHB quanta.<br />

1010 Preemptive, re-arbitrate after 1024 AHB quanta.<br />

1011 Preemptive, re-arbitrate after 2048 AHB quanta.<br />

1100 Preemptive, re-arbitrate after 4096 AHB quanta.<br />

1101 Preemptive, re-arbitrate after 8192 AHB quanta.<br />

1110 Preemptive, re-arbitrate after 16384 AHB quanta.<br />

1111 Non- preemptive, infinite AHB quanta.<br />

11:8 default_master 0001 Master 1 (CPU) is the default master. 0001<br />

15:12 EP1 0010 External priority for master 1 (CPU) is tbd. tbd<br />

19:16 EP2 0001 External priority for master 2 (AHB1) is tbd. tbd<br />

<strong>UM10211</strong>_1<br />

© NXP B.V. 2007. All rights reserved.<br />

User manual Rev. 01 — 27 March 2007 30 of 613

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