UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 11: LPC2300 Ethernet
Table 165. Transmit Status Vector 0 register (TSV0 - address 0xFFE0 0158) bit description
Bit Symbol Function Reset
value
27:12 Total bytes The total number of bytes transferred including collided 0x0
attempts.
28 Control frame The frame was a control frame. 0
29 Pause The frame was a control frame with a valid PAUSE 0
opcode.
30 Backpressure Carrier-sense method backpressure was previously 0
applied.
31 VLAN Frame’s length/type field contained 0x8100 which is the
VLAN protocol identifier.
0
[1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or
ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length
out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the
status of the received frame.
11.14 Transmit Status Vector 1 Register (TSV1 - 0xFFE0 015C)
The Transmit Status Vector 1 register (TSV1) is a Read Only register with an address of
0xFFE0 015C. The transmit status vector registers store the most recent transmit status
returned by the MAC. Since the status vector consists of more than 4 bytes, status is
distributed over two registers TSV0 and TSV1. These registers are provided for debug
purposes, because the communication between driver software and the Ethernet block
takes place primarily through the frame descriptors. The status register contents are valid
as long as the internal status of the MAC is valid and should typically only be read when
the transmit and receive processes are halted.Table 11–166 lists the bit definitions of the
TSV1 register.
Table 166. Transmit Status Vector 1 register (TSV1 - address 0xFFE0 015C) bit description
Bit Symbol Function Reset
value
15:0 Transmit byte count The total number of bytes in the frame, not counting the
collided bytes.
0x0
19:16 Transmit collision
count
Number of collisions the current packet incurred during
transmission attempts. The maximum number of collisions
(16) cannot be represented.
31:20 - Unused 0x0
0x0
11.15 Receive Status Vector Register (RSV - 0xFFE0 0160)
The Receive status vector register (RSV) is a Read Only register with an address of
0xFFE0 0160. The receive status vector register stores the most recent receive status
returned by the MAC. This register is provided for debug purposes, because the
communication between driver software and the Ethernet block takes place primarily
through the frame descriptors. The status register contents are valid as long as the
internal status of the MAC is valid and should typically only be read when the transmit and
receive processes are halted.
Table 11–167 lists the bit definitions of the RSV register.
UM10211_1
© NXP B.V. 2007. All rights reserved.
User manual Rev. 01 — 27 March 2007 156 of 613