UM10211 - Standard ICs

UM10211
Chapter 7: Vectored Interrupt Controller (VIC)
Rev. 01 — 27 March 2007
User manual
1. Features
• ARM PrimeCell Vectored Interrupt Controller
• Mapped to AHB address space for fast access
• Supports 32 vectored IRQ interrupts
• 16 programmable interrupt priority levels
• Fixed hardware priority within each programmable priority level
• Hardware priority level masking
• Any input can be assigned as an FIQ interrupt
• Software interrupt generation
2. Description
3. Register description
The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast
Interrupt reQuest (FIQ). The Vectored Interrupt Controller (VIC) takes 32 interrupt request
inputs and programmably assigns them as FIQ or vectored IRQ types. The programmable
assignment scheme means that priorities of interrupts from the various peripherals can be
dynamically assigned and adjusted.
Fast Interrupt reQuest (FIQ) requests have the highest priority. If more than one request is
assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM
processor. The fastest possible FIQ latency is achieved when only one request is
classified as FIQ, because then the FIQ service routine can simply start dealing with that
device. But if more than one request is assigned to the FIQ class, the FIQ service routine
can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an
interrupt.
Vectored IRQ’s, which include all interrupt requests that are not classified as FIQs, have a
programmable interrupt priority. When more than one interrupt is assigned the same
priority and occur simultaneously, the one connected to the lowest numbered VIC channel
(see Table 7–77 on page 83) will be serviced first.
The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the
ARM processor. The IRQ service routine can start by reading a register from the VIC and
jumping to the address supplied by that register.
The VIC implements the registers shown in Table 7–63. More detailed descriptions follow.
UM10211_1
© NXP B.V. 2007. All rights reserved.
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