UM10211 - Standard ICs

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NXP Semiconductors UM10211 Chapter 11: LPC2300 Ethernet All of the above interrupts can be enabled and disabled by setting or resetting the corresponding bits in the IntEnable register. Enabling or disabling does not affect the IntStatus register contents, only the propagation of the interrupt status to the CPU (via the Vectored Interrupt Controller). The interrupts, either of individual frames or of the whole list, are a good means of communication between the DMA manager and the device driver, triggering the device driver to inspect the status words of descriptors that have been processed. Transmit example Figure 11–22 illustrates the transmit process in an example transmitting uses a frame header of 8 bytes and a frame payload of 12 bytes. TxDescriptor 0x7FE010EC 0x7FE01314 0x7FE0131B TxStatus 0x7FE011F8 descriptor array 0x7FE010EC 0x7FE010F0 0x7FE010F4 0x7FE010F8 0x7FE010FC 0x7FE0100 Packet 0x7FE01314 00 CONTROL Control 7 Packet 0x7FE01411 0 0 CONTROL Control 7 Packet 0x7FE01419 1 1 CONTROL Control 3 descriptor 0 descriptor 1 descriptor 2 PACKET 0 HEADER (8 bytes) 0x7FE01411 0x7FE01419 0x7FE0141C PACKET 0 PAYLOAD (12 bytes) 0x7FE01324 0x7FE0132B TxProduceIndex status 1 status 0 status 3 status 2 StatusInfo StatusInfo StatusInfo StatusInfo 0x7FE011F8 0x7FE011FC 0x7FE01200 0x7FE01204 status array 0x7FE0104 0x7FE01108 Packet 0x7FE01324 0 0 CONTROL Control 7 descriptor 3 PACKET 1 HEADER (8 bytes) TxConsumeIndex TxDescriptorNumber = 3 descriptor array fragment buffers status array Fig 22. Transmit example memory and registers After reset the values of the DMA registers will be zero. During initialization the device driver will allocate the descriptor and status array in memory. In this example, an array of four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address boundary. Since the number of descriptors matches the number of statuses the status array consists of four elements; the array is 4x1x4 bytes and aligned on a 4 byte address boundary. The device driver writes the base address of the descriptor array (0x7FE0 10EC) to the TxDescriptor register and the base address of the status array UM10211_1 © NXP B.V. 2007. All rights reserved. User manual Rev. 01 — 27 March 2007 178 of 613
NXP Semiconductors UM10211 Chapter 11: LPC2300 Ethernet (0x7FE0 11F8) to the TxStatus register. The device driver writes the number of descriptors and statuses minus 1(3) to the TxDescriptorNumber register. The descriptors and statuses in the arrays need not be initialized, yet. At this point, the transmit datapath may be enabled by setting the TxEnable bit in the Command register. If the transmit datapath is enabled while there are no further frames to send the TxFinishedInt interrupt flag will be set. To reduce the processor interrupt load only the desired interrupts can be enabled by setting the relevant bits in the IntEnable register. Now suppose application software wants to transmit a frame of 12 bytes using a TCP/IP protocol (in real applications frames will be larger than 12 bytes). The TCP/IP stack will add a header to the frame. The frame header need not be immediately in front of the payload data in memory. The device driver can program the Tx DMA to collect header and payload data. To do so, the device driver will program the first descriptor to point at the frame header; the Last flag in the descriptor will be set to false/0 to indicate a multi-fragment transmission. The device driver will program the next descriptor to point at the actual payload data. The maximum size of a payload buffer is 2 kB so a single descriptor suffices to describe the payload buffer. For the sake of the example though the payload is distributed across two descriptors. After the first descriptor in the array describing the header, the second descriptor in the array describes the initial 8 bytes of the payload; the third descriptor in the array describes the remaining 4 bytes of the frame. In the third descriptor the Last bit in the Control word is set to true/1 to indicate it is the last descriptor in the frame. In this example the Interrupt bit in the descriptor Control field is set in the last fragment of the frame in order to trigger an interrupt after the transmission completed. The Size field in the descriptor’s Control word is set to the number of bytes in the fragment buffer, -1 encoded. Note that in real device drivers, the payload will typically only be split across multiple descriptors if it is more than 2 kB. Also note that transmission payload data is forwarded to the hardware without the device driver copying it (zero copy device driver). After setting up the descriptors for the transaction the device driver increments the TxProduceIndex register by 3 since three descriptors have been programmed. If the transmit datapath was not enabled during initialization the device driver needs to enable the datapath now. If the transmit datapath is enabled the Ethernet block will start transmitting the frame as soon as it detects the TxProduceIndex is not equal to TxConsumeIndex - both were zero after reset. The Tx DMA will start reading the descriptors from memory. The memory system will return the descriptors and the Ethernet block will accept them one by one while reading the transmit data fragments. As soon as transmission read data is returned from memory, the Ethernet block will try to start transmission on the Ethernet connection via the (R)MII interface. After transmitting each fragment of the frame the Tx DMA will write the status of the fragment’s transmission. Statuses for all but the last fragment in the frame will be written as soon as the data in the frame has been accepted by the Tx DMA manager. The status for the last fragment in the frame will only be written after the transmission has completed on the Ethernet connection. UM10211_1 © NXP B.V. 2007. All rights reserved. User manual Rev. 01 — 27 March 2007 179 of 613
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UM10211 - Standard ICs

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