UM10211 - Standard ICs

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UM10211 Chapter 14: Universal Asynchronous Receiver Transmitter (UART) 0, 2, 3 Rev. 01 — 27 March 2007 User manual 1. Features 2. Pin description • 16 byte Receive and Transmit FIFOs. • Register locations conform to ‘550 industry standard. • Receiver FIFO trigger points at 1, 4, 8, and 14 bytes. • Built-in baud rate generator. • Fractional divider for baud rate control, autobaud capabilities and mechanism that enables software flow control implementation. • In addition, UART3 includes an IrDA mode to support infrared communication. Table 302: UART0 Pin description Pin Type Description RXD0, RXD2, RXD3 Input Serial Input. Serial receive data. TXD0, TXD2, TXD3 Output Serial Output. Serial transmit data. 3. Register description Each UART contains registers as shown in Table 14–303. The Divisor Latch Access Bit (DLAB) is contained in UnLCR7 and enables access to the Divisor Latches. UM10211_1 © NXP B.V. 2007. All rights reserved. User manual Rev. 01 — 27 March 2007 322 of 613
User manual Rev. 01 — 27 March 2007 323 of 613 UM10211_1 © NXP B.V. 2007. All rights reserved. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 303: UART Register Map Generic Name RBR (DLAB=0) THR (DLAB=0) DLL (DLAB=1) DLM (DLAB=1) IER (DLAB=0) IIR FCR LCR LSR SCR ACR Description Bit functions and addresses Access Reset MSB LSB value [ 1] BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Receiver Buffer Register Transmit Holding Register UARTn Register Name & Address 8 bit Read Data RO NA U0RBR - 0xE000 C000 U2RBR - 0xE007 8000 U3RBR - 0xE007 C000 8 bit Write Data WO NA U0THR - 0xE000 C000 U2THR - 0xE007 8000 U3THR - 0xE007 C000 Divisor Latch LSB 8 bit Data R/W 0x01 U0DLL - 0xE000 C000 U2DLL - 0xE007 8000 U3DLL - 0xE007 C000 Divisor Latch MSB Interrupt Enable Register Interrupt ID Register FIFO Control Register Line Control Register Line Status Register Scratch Pad Register Auto-baud Control Register Reserved 8 bit Data R/W 0x00 U0DLM - 0xE000 C004 U2DLM - 0xE007 8004 U3DLM - 0xE007 C004 0 Enable RX Line Status Interrupt Enable Auto- Baud Time- Out Interrupt Enable THRE Interrupt Enable End of Auto- Baud Interrupt Enable RX Data Available Interrupt R/W 0x00 U0IER - 0xE000 C004 U2IER - 0xE007 8004 U3IER - 0xE007 C004 Reserved ABTOInt ABEOint RO 0x01 U0IIR - 0xE000 C008 FIFOs Enabled 0 IIR3 IIR2 IIR1 IIR0 U2IIR - 0xE007 8008 U3IIR - 0xE007 C008 RX Trigger Reserved TX FIFO Reset DLAB Set Break Stick Parity RX FIFO Error Even Parity Select Parity Enable Number of Stop Bits RX FIFO Reset FIFO Enable WO 0x00 U0FCR - 0xE000 C008 U2FCR - 0xE007 8008 U3FCR - 0xE007 C008 Word Length Select R/W 0x00 U0LCR - 0xE000 C00C U2LCR - 0xE007 800C U3LCR - 0xE007 C00C TEMT THRE BI FE PE OE DR RO 0x60 U0LSR - 0xE000 C014 U2LSR - 0xE007 8014 U3LSR - 0xE007 C014 8 bit Data R/W 0x00 U0SCR - 0xE000 C01C U2SCR - 0xE007 801C U3SCR - 0xE007 C01C Reserved [31:10] ABTO IntClr ABEO IntClr R/W 0x00 U0ACR - 0xE000 C020 Reserved [7:3] Auto Reset Mode Start U2ACR - 0xE007 8020 U3ACR - 0xE007 C020 Chapter 14: LPC2300 UART0, 2, 3 NXP Semiconductors UM10211
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UM10211 LPC2364/66/68/78 User manua
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UM10211 Chapter 10: General Purpose
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UM10211 Chapter 23: Pulse Width Mod
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UM10211 Chapter 32: Supplementary i
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UM10211 - Standard ICs

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