UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 2: LPC2300 Memory map
4.2 Memory re-mapping
5. Memory mapping control
In order to allow for compatibility with future derivatives, the entire Boot ROM is mapped
to the top of the on-chip memory space. In this manner, the use of larger or smaller flash
modules will not require changing the location of the Boot ROM (which would require
changing the Boot Loader code itself) or changing the mapping of the Boot ROM interrupt
vectors. Memory spaces other than the interrupt vectors remain in fixed locations.
Figure 2–7 shows the on-chip memory mapping in the modes defined above.
The portion of memory that is re-mapped to allow interrupt processing in different modes
includes the interrupt vector area (32 bytes) and an additional 32 bytes for a total of
64 bytes, that facilitates branching to interrupt handlers at distant physical addresses. The
remapped code locations overlay addresses 0x0000 0000 through 0x0000 003F. A typical
user program in the Flash memory can place the entire FIQ handler at address
0x0000 001C without any need to consider memory boundaries. The vector contained in
the SRAM, external memory, and Boot ROM must contain branches to the actual interrupt
handlers, or to other instructions that accomplish the branch to the interrupt handlers.
There are three reasons this configuration was chosen:
1. To give the FIQ handler in the Flash memory the advantage of not having to take a
memory boundary caused by the remapping into account.
2. Minimize the need to for the SRAM and Boot ROM vectors to deal with arbitrary
boundaries in the middle of code space.
3. To provide space to store constants for jumping beyond the range of single word
branch instructions.
Re-mapped memory areas, including the Boot ROM and interrupt vectors, continue to
appear in their original location in addition to the re-mapped address.
Details on re-mapping and examples can be found in Section 2–5 “Memory mapping
control” on page 17.
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. This allows code running in different memory spaces
to have control of the interrupts.
5.1 Memory Mapping Control Register (MEMMAP - 0xE01F C040)
Whenever an exception handling is necessary, microcontroller will fetch an instruction
residing on exception corresponding address as described in Table 2–5 “ARM exception
vector locations” on page 16. The MEMMAP register determines the source of data that
will fill this table.
Table 7.
Memory mapping control registers
Name Description Access Reset Address
value
MEMMAP Memory mapping control. Selects whether the
ARM interrupt vectors are read from the Boot
ROM, User Flash, or RAM.
R/W 0x00 0xE01F C040
UM10211_1
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User manual Rev. 01 — 27 March 2007 17 of 613