UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 4: LPC2300 Clocking and power control
The PM2, PM1, and PM0 bits in PCON allow entering reduced power modes as needed.
The encoding of these bits allows backward compatibility with devices that previously only
supported Idle and Power Down modes. Table 4–41 below shows the encoding for the
four reduced power modes supported by the LPC2300.
Table 41. Encoding of reduced power modes
PM2, PM1, PM0 Description
000 Normal operation
001 Idle mode. Causes the processor clock to be stopped, while on-chip peripherals
remain active. Any enabled interrupt from a peripheral or an external interrupt
source will cause the processor to resume execution. See text for details.
101 Sleep mode. This mode is similar to Power Down mode (the oscillator and all
on-chip clocks are stopped), but the Flash memory is left in Standby mode. This
allows a more rapid wakeup than Power Down mode because the Flash
reference voltage regulator start-up time is not needed. See text for details.
010 Power Down mode. Causes the oscillator and all on-chip clocks to be stopped.
A wakeup condition from an external interrupt can cause the oscillator to
re-start, the PD bit to be cleared, and the processor to resume execution. See
text for details.
110 Reserved.
Others
Reserved, not currently used.
7.7 Interrupt Wakeup Register (INTWAKE - 0xE01F C144)
Enable bits in the INTWAKE register allow the external interrupts to wake up the
processor if it is in Power Down mode. The related EINTn function must be mapped to the
pin in order for the wakeup process to take place. It is not necessary for the interrupt to be
enabled in the Vectored Interrupt Controller for a wakeup to take place. This arrangement
allows additional capabilities, such as having an external interrupt input wake up the
processor from Power Down mode without causing an interrupt (simply resuming
operation), or allowing an interrupt to be enabled during Power Down without waking the
processor up if it is asserted (eliminating the need to disable the interrupt if the wakeup
feature is not desirable in the application). Details of the wakeup operations are shown in
Table 4–42.
For an external interrupt pin to be a source that would wake up the microcontroller from
Power-down mode, it is also necessary to clear the corresponding interrupt flag (see
Section 3–6.2 “External Interrupt flag register (EXTINT - 0xE01F C140)”).
Table 42. Interrupt Wakeup register (INTWAKE - address 0xE01F C144) bit description
Bit Symbol Description Reset
value
0 EXTWAKE0 When one, assertion of EINT0 will wake up the processor from 0
Power Down mode.
1 EXTWAKE1 When one, assertion of EINT1 will wake up the processor from 0
Power Down mode.
2 EXTWAKE2 When one, assertion of EINT2 will wake up the processor from 0
Power Down mode.
3 EXTWAKE3 When one, assertion of EINT3 will wake up the processor from
Power Down mode.
0
UM10211_1
© NXP B.V. 2007. All rights reserved.
User manual Rev. 01 — 27 March 2007 51 of 613