UM10211 - Standard ICs

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NXP Semiconductors UM10211 Chapter 3: LPC2300 System control More details on power-down mode will be discussed in the following chapters. 0 Table 13. External Interrupt Flag register (EXTINT - address 0xE01F C140) bit description Bit Symbol Description Reset value 0 EINT0 In level-sensitive mode, this bit is set if the EINT0 function is selected for its the pin is in its active state. [1] pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when 1 EINT1 In level-sensitive mode, this bit is set if the EINT1 function is selected for its 0 pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. [1] 2 EINT2 In level-sensitive mode, this bit is set if the EINT2 function is selected for its 0 pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. [1] 3 EINT3 In level-sensitive mode, this bit is set if the EINT3 function is selected for its 0 pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. [1] 7:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1] Example: e.g. if the EINTx is selected to be low level sensitive and low level is present on corresponding pin, this bit can not be cleared; this bit can be cleared only when signal on the pin becomes high. 6.3 External Interrupt Mode register (EXTMODE - 0xE01F C148) The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins that are selected for the EINT function (see chapter Pin Connect Block on page 105) and enabled in the VICIntEnable register (Section 7–4.4 “Interrupt Enable Register (VICIntEnable - 0xFFFF F010)”) can cause interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions). Note: Software should only change a bit in this register when its interrupt is disabled in VICIntEnable, and should write the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could be set by changing the mode and not having the EXTINT cleared. NA UM10211_1 © NXP B.V. 2007. All rights reserved. User manual Rev. 01 — 27 March 2007 26 of 613
NXP Semiconductors UM10211 Chapter 3: LPC2300 System control Table 14. External Interrupt Mode register (EXTMODE - address 0xE01F C148) bit description Bit Symbol Value Description Reset value 0 EXTMODE0 0 Level-sensitivity is selected for EINT0. 0 1 EINT0 is edge sensitive. 1 EXTMODE1 0 Level-sensitivity is selected for EINT1. 0 1 EINT1 is edge sensitive. 2 EXTMODE2 0 Level-sensitivity is selected for EINT2. 0 1 EINT2 is edge sensitive. 3 EXTMODE3 0 Level-sensitivity is selected for EINT3. 0 1 EINT3 is edge sensitive. 7:4 - - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 6.4 External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C) In level-sensitive mode, the bits in this register select whether the corresponding pin is high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or falling-edge sensitive. Only pins that are selected for the EINT function (see "Pin Connect Block" chapter on page 105) and enabled in the VICIntEnable register (Section 7–4.4 “Interrupt Enable Register (VICIntEnable - 0xFFFF F010)”) can cause interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions). Note: Software should only change a bit in this register when its interrupt is disabled in VICIntEnable, and should write the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could be set by changing the polarity and not having the EXTINT cleared. Table 15. External Interrupt Polarity register (EXTPOLAR - address 0xE01F C14C) bit description Bit Symbol Value Description Reset value 0 EXTPOLAR0 0 EINT0 is low-active or falling-edge sensitive (depending on 0 EXTMODE0). 1 EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0). 1 EXTPOLAR1 0 EINT1 is low-active or falling-edge sensitive (depending on 0 EXTMODE1). 1 EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1). 2 EXTPOLAR2 0 EINT2 is low-active or falling-edge sensitive (depending on 0 EXTMODE2). 1 EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2). UM10211_1 © NXP B.V. 2007. All rights reserved. User manual Rev. 01 — 27 March 2007 27 of 613
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UM10211 - Standard ICs

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