UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 32: Supplementary information
5.10 PLL and Power down mode . . . . . . . . . . . . . . 41
5.11 PLL frequency calculation . . . . . . . . . . . . . . . 41
5.12 Procedure for determining PLL settings . . . . . 42
5.13 Examples of PLL settings . . . . . . . . . . . . . . . . 43
5.14 PLL setup sequence. . . . . . . . . . . . . . . . . . . . 44
6 Clock dividers . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.1 CPU Clock Configuration register (CCLKCFG -
0xE01F C104) . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2 USB Clock Configuration register (USBCLKCFG -
0xE01F C108) . . . . . . . . . . . . . . . . . . . . . . . . 46
6.3 IRC Trim Register (IRCTRIM - 0xE01F C1A4) 46
6.4 Peripheral Clock Selection registers 0 and 1
(PCLKSEL0 - 0xE01F C1A8 and PCLKSEL1 -
0xE01F C1AC) . . . . . . . . . . . . . . . . . . . . . . . . 46
Chapter 5: External Memory Controller (EMC)
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3 Functional overview . . . . . . . . . . . . . . . . . . . . 56
4 EMC functional description . . . . . . . . . . . . . . 56
5 AHB Slave register interface. . . . . . . . . . . . . . 57
5.1 AHB Slave memory interface . . . . . . . . . . . . . 57
5.1.1 Memory transaction endianness. . . . . . . . . . . 58
5.1.2 Memory transaction size. . . . . . . . . . . . . . . . . 58
5.1.3 Write protected memory areas . . . . . . . . . . . . 58
5.2 Data buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.2.1 Write buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.2.2 Read buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3 Memory controller state machine . . . . . . . . . . 59
5.4 Pad interface . . . . . . . . . . . . . . . . . . . . . . . . . 59
6 Memory bank select . . . . . . . . . . . . . . . . . . . . 59
7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8 Pin description. . . . . . . . . . . . . . . . . . . . . . . . . 60
9 Register description . . . . . . . . . . . . . . . . . . . . 60
9.1 EMC Control Register (EMCControl -
0xFFE0 8000). . . . . . . . . . . . . . . . . . . . . . . . . 61
7 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.3 Power Down mode. . . . . . . . . . . . . . . . . . . . . 49
7.4 Peripheral power control . . . . . . . . . . . . . . . . 49
7.5 Register description . . . . . . . . . . . . . . . . . . . . 49
7.6 Power Mode Control register (PCON -
0xE01F C0C0) . . . . . . . . . . . . . . . . . . . . . . . . 50
7.7 Interrupt Wakeup Register (INTWAKE -
0xE01F C144) . . . . . . . . . . . . . . . . . . . . . . . . 51
7.8 Power Control for Peripherals register (PCONP -
0xE01F COC4) . . . . . . . . . . . . . . . . . . . . . . . 52
7.9 Power control usage notes . . . . . . . . . . . . . . 54
7.10 Power domains . . . . . . . . . . . . . . . . . . . . . . . 54
8 Wakeup timer. . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.2 EMC Status Register (EMCStatus - 0xFFE0 8004)
62
9.3 EMC Configuration Register (EMCConfig -
0xFFE0 8008) . . . . . . . . . . . . . . . . . . . . . . . . 62
9.4 Static Memory Configuration Registers
(EMCStaticConfig0-1 - 0xFFE0 8200, 220) . . 63
9.5 Static Memory Write Enable Delay Registers
(EMCStaticWaitWen0-1 - 0xFFE0 8204, 224) 64
9.6 Static Memory Output Enable Delay Registers
(EMCStaticWaitOen0-1 - 0xFFE0 8208, 228) 65
9.7 Static Memory Read Delay Registers
(EMCStaticWaitRd0-1 - 0xFFE0 820C, 22C) . 65
9.8 Static Memory Page Mode Read Delay Registers
(EMCStaticwaitPage0-1 - 0xFFE0 8210, 230) 66
9.9 Static Memory Write Delay Registers
(EMCStaticWaitwr0-1 - 0xFFE0 8214, 234) . . 66
9.10 Static Memory Extended Wait Register
(EMCStaticExtendedWait - 0xFFE0 8880). . . 67
9.11 Static Memory Turn Round Delay Registers
(EMCStaticWaitTurn0-1 - 0xFFE0 8218, 238, 258,
278) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Chapter 6: Memory Acceleration Module (MAM)
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3 Memory Acceleration Module blocks. . . . . . . 70
3.1 Flash memory bank . . . . . . . . . . . . . . . . . . . . 70
3.2 Instruction latches and data latches . . . . . . . . 71
3.3 Flash programming Issues . . . . . . . . . . . . . . . 71
4 Memory Accelerator Module Operating modes .
71
5 MAM configuration . . . . . . . . . . . . . . . . . . . . . 72
6 Register description . . . . . . . . . . . . . . . . . . . . 72
7 MAM Control Register (MAMCR - 0xE01F C000)
73
8 MAM Timing Register (MAMTIM - 0xE01F C004)
73
9 MAM usage notes . . . . . . . . . . . . . . . . . . . . . . 75
continued >>
UM10211_1
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User manual Rev. 01 — 27 March 2007 598 of 613