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UM10211 - Standard ICs

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NXP Semiconductors<br />

<strong>UM10211</strong><br />

Chapter 11: LPC2300 Ethernet<br />

Table 152. Station Address register (SA2 - address 0xFFE0 0048) bit description<br />

Bit Symbol Function Reset<br />

value<br />

7:0 STATION ADDRESS, This field holds the sixth octet of the station address. 0x0<br />

6th octet<br />

15:8 STATION ADDRESS, This field holds the fifth octet of the station address. 0x0<br />

5th octet<br />

31:16 - Unused 0x0<br />

The station address is used for perfect address filtering and for sending pause control<br />

frames. For the ordering of the octets in the packet please refer to Figure 11–19.<br />

11. Control register definitions<br />

11.1 Command Register (Command - 0xFFE0 0100)<br />

The Command register (Command) register has an address of 0xFFE0 0100. Its bit<br />

definition is shown in Table 11–153.<br />

Table 153. Command register (Command - address 0xFFE0 0100) bit description<br />

Bit Symbol Function Reset<br />

value<br />

0 RxEnable Enable receive. 0<br />

1 TxEnable Enable transmit. 0<br />

2 - Unused 0x0<br />

3 RegReset When a ’1’ is written, all datapaths and the host registers are 0<br />

reset. The MAC needs to be reset separately.<br />

4 TxReset When a ’1’ is written, the transmit datapath is reset. 0<br />

5 RxReset When a ’1’ is written, the receive datapath is reset. 0<br />

6 PassRuntFrame When set to ’1’, passes runt frames smaller than 64 bytes to<br />

memory unless they have a CRC error. If ’0’ runt frames are<br />

filtered out.<br />

0<br />

7 PassRxFilter When set to ’1’, disables receive filtering i.e. all frames 0<br />

received are written to memory.<br />

8 TxFlowControl Enable IEEE 802.3 / clause 31 flow control sending pause 0<br />

frames in full duplex and continuous preamble in half duplex.<br />

9 RMII When set to ’1’, RMII mode is selected; if ’0’, MII mode is 0<br />

selected.<br />

10 FullDuplex When set to ’1’, indicates full duplex operation. 0<br />

31:11 - Unused 0x0<br />

All bits can be written and read. The Tx/RxReset bits are write only, reading will return a 0.<br />

11.2 Status Register (Status - 0xFFE0 0104)<br />

The Status register (Status) is a Read Only register with an address of 0xFFE0 0104. Its<br />

bit definition is shown in Table 11–154.<br />

<strong>UM10211</strong>_1<br />

© NXP B.V. 2007. All rights reserved.<br />

User manual Rev. 01 — 27 March 2007 150 of 613

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