UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 12: LPC2300 CAN1, 2
Table 212. Central Transit Status Register (CANTxSR - address 0xE004 0000) bit description
Bit Symbol Description Reset
Value
15:10 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
16 TCS1 When 1, all requested transmissions have been completed successfully
by the CAN1 controller (same as TCS in CAN1GSR).
17:16 TCS2 When 1, all requested transmissions have been completed successfully
by the CAN2 controller (same as TCS in CAN2GSR).
31:18 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
1
1
NA
8.2 Central Receive Status Register (CANRxSR - 0xE004 0004)
Table 213. Central Receive Status Register (CANRxSR - address 0xE004 0004) bit
description
Bit Symbol Description Reset
Value
0 RS1 When 1, CAN1 is receiving a message (same as RS in CAN1GSR). 0
1 RS2 When 1, CAN2 is receiving a message (same as RS in CAN2GSR). 0
7:2 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
8 RB1 When 1, a received message is available in the CAN1 controller (same 0
as RBS in CAN1GSR).
9 RB2 When 1, a received message is available in the CAN2 controller (same 0
as RBS in CAN2GSR).
15:10 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
16 DOS1 When 1, a message was lost because the preceding message to CAN1 0
controller was not read out quickly enough (same as DOS in CAN1GSR).
17:16 DOS2 When 1, a message was lost because the preceding message to CAN2 0
controller was not read out quickly enough (same as DOS in CAN2GSR).
31:18 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
8.3 Central Miscellaneous Status Register (CANMSR - 0xE004 0008)
Table 214. Central Miscellaneous Status Register (CANMSR - address 0xE004 0008) bit
description
Bit Symbol Description Reset
Value
0 E1 When 1, one or both of the CAN1 Tx and Rx Error Counters has reached 0
the limit set in the CAN1EWL register (same as ES in CAN1GSR)
1 E2 When 1, one or both of the CAN2 Tx and Rx Error Counters has reached 0
the limit set in the CAN2EWL register (same as ES in CAN2GSR)
7:2 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
UM10211_1
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User manual Rev. 01 — 27 March 2007 233 of 613