UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 4: LPC2300 Clocking and power control
5.5 PLL Configuration register (PLLCFG - 0xE01F C084)
The PLLCFG register contains the PLL multiplier and divider values. Changes to the
PLLCFG register do not take effect until a correct PLL feed sequence has been given (see
Section 4–5.9 “PLL Feed register (PLLFEED - 0xE01F C08C)”). Calculations for the PLL
frequency, and multiplier and divider values are found in the Section 4–5.11 “PLL
frequency calculation”.
Table 26.
PLL Configuration register (PLLCFG - address 0xE01F C084) bit description
Bit Symbol Description Reset
value
14:0 MSEL PLL Multiplier value. Supplies the value "M" in the PLL frequency
calculations. The value stored here is M - 1.
Note: Not all values of M are needed, and therefore some are not
supported by hardware. For details on selecting values for MSEL see
Section 4–5.11 “PLL frequency calculation”.
0
15 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
23:16 NSEL PLL Pre-Divider value. Supplies the value "N" in the PLL frequency
calculations. The value stored here is N - 1, giving a range for N of 1
through 256.
Note: For details on selecting the right value for NSEL see Section
4–5.11 “PLL frequency calculation”.
31:24 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
0
NA
5.6 PLL Status register (PLLSTAT - 0xE01F C088)
The read-only PLLSTAT register provides the actual PLL parameters that are in effect at
the time it is read, as well as the PLL status. PLLSTAT may disagree with values found in
PLLCON and PLLCFG because changes to those registers do not take effect until a
proper PLL feed has occurred (see Section 4–5.9 “PLL Feed register (PLLFEED -
0xE01F C08C)”).
Table 27.
PLL Status register (PLLSTAT - address 0xE01F C088) bit description
Bit Symbol Description Reset
value
14:0 MSEL Read-back for the PLL Multiplier value. This is the value currently 0
used by the PLL, and is one less than the actual multiplier.
15 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
23:16 NSEL Read-back for the PLL Pre-Divider value. This is the value currently 0
used by the PLL, and is one less than the actual divider.
24 PLLE Read-back for the PLL Enable bit. When one, the PLL is currently
activated. When zero, the PLL is turned off. This bit is automatically
cleared when Power Down mode is activated.
0
UM10211_1
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User manual Rev. 01 — 27 March 2007 39 of 613