UM10211 - Standard ICs

NXP Semiconductors
UM10211
Chapter 32: Supplementary information
Table 57. Static Memory Turn Round Delay registers0-1
(EMCStaticWaitTurn0-1- addresses
0xFFE0 8218, 0xFFE0 8238) bit description . .68
Table 58. MAM responses to program accesses of various
types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 59. MAM responses to data and DMA accesses of
various types . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 60. Summary of Memory Acceleration Module
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 61. MAM Control Register (MAMCR - address
0xE01F C000) bit description . . . . . . . . . . . . . .73
Table 62. MAM Timing register (MAMTIM - address
0xE01F C004) bit description . . . . . . . . . . . . . .74
Table 63. VIC register map. . . . . . . . . . . . . . . . . . . . . . . .77
Table 64. Software Interrupt register (VICSoftInt - address
0xFFFF F018) bit description . . . . . . . . . . . . . .79
Table 65. Software Interrupt Clear register (VICSoftIntClear
- address 0xFFFF F01C) bit description. . . . . .79
Table 66. Raw Interrupt Status register (VICRawIntr -
address 0xFFFF F008) bit description . . . . . . .80
Table 67. Interrupt Enable register (VICIntEnable - address
0xFFFF F010) bit description . . . . . . . . . . . . . .80
Table 68. Interrupt Enable Clear register (VICIntEnClear -
address 0xFFFF F014) bit description . . . . . . .80
Table 69. Interrupt Select register (VICIntSelect - address
0xFFFF F00C) bit description. . . . . . . . . . . . . .81
Table 70. IRQ Status register (VICIRQStatus - address
0xFFFF F000) bit description . . . . . . . . . . . . . .81
Table 71. FIQ Status register (VICFIQStatus - address
0xFFFF F004) bit description . . . . . . . . . . . . . .81
Table 72. Vector Address registers 0-31 (VICVectAddr0-31 -
addresses 0xFFFF F100 to 0xFFFF F17C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 73. Vector Priority registers 0-31 (VICVectPriority0-31
- addresses 0xFFFF F200 to 0xFFFF F27C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 74. Vector Address register (VICAddress - address
0xFFFF FF00) bit description . . . . . . . . . . . . . .82
Table 75. Software Priority Mask register
(VICSWPriorityMask - address 0xFFFF F024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 76. Protection Enable register (VICProtection -
address 0xFFFF F020) bit description . . . . . . .83
Table 77. Connection of interrupt sources to the Vectored
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . .83
Table 78. Interrupt sources bit allocation table. . . . . . . . .85
Table 79. LPC2364/66/68 pin description . . . . . . . . . . . .87
Table 80. LPC2378 pin description . . . . . . . . . . . . . . . . .95
Table 81. Pin function select register bits. . . . . . . . . . . .105
Table 82. Pin Mode Select register Bits . . . . . . . . . . . . .106
Table 83. Pin Connect Block Register Map . . . . . . . . . .106
Table 84. Pin function select register 0 (PINSEL0 - address
0xE002 C000) bit description. . . . . . . . . . . . . 107
Table 85. Pin function select register 1 (PINSEL1 - address
0xE002 C004) bit description. . . . . . . . . . . . . 107
Table 86. Pin function select register 2 (PINSEL2 - address
0xE002 C008) bit description. . . . . . . . . . . . . 108
Table 87. Pin function select register 3 (PINSEL3 - address
0xE002 C00C) bit description . . . . . . . . . . . . 109
Table 88. Pin function select register 4 (PINSEL4 - address
0xE002 C010) bit description. . . . . . . . . . . . . 109
Table 89. Pin function select register 5 (PINSEL5 - address
0xE002 C014) bit description. . . . . . . . . . . . . 110
Table 90. Pin function select register 6 (PINSEL6 - address
0xE002 C018) bit description. . . . . . . . . . . . . 111
Table 91. Pin function select register 7 (PINSEL7 - address
0xE002 C01C) bit description . . . . . . . . . . . . 111
Table 92. Pin function select register 8 (PINSEL8 - address
0xE002 C020) bit description. . . . . . . . . . . . . 112
Table 93. Pin function select register 9 (PINSEL9 - address
0xE002 C024) bit description. . . . . . . . . . . . . 113
Table 94. Pin function select register 10 (PINSEL10 -
address 0xE002 C028) bit description . . . . . . 113
Table 95. Pin Mode select register 0 (PINMODE0 - address
0xE002 C040) bit description. . . . . . . . . . . . . 114
Table 96. Pin Mode select register 1 (PINMODE1 - address
0xE002 C044) bit description. . . . . . . . . . . . . 114
Table 97. Pin Mode select register 2 (PINMODE2 - address
0xE002 C048) bit description. . . . . . . . . . . . . 114
Table 98. Pin Mode select register 3 (PINMODE3 - address
0xE002 C04C) bit description . . . . . . . . . . . . 115
Table 99. Pin Mode select register 4 (PINMODE4 - address
0xE002 C050) bit description. . . . . . . . . . . . . 115
Table 100.Pin Mode select register 5 (PINMODE5 - address
0xE002 C054) bit description. . . . . . . . . . . . . 115
Table 101.Pin Mode select register 6 (PINMODE6 - address
0xE002 C058) bit description. . . . . . . . . . . . . 115
Table 102.Pin Mode select register 7 (PINMODE7 - address
0xE002 C05C) bit description . . . . . . . . . . . . 116
Table 103.Pin Mode select register 8 (PINMODE8 - address
0xE002 C060) bit description. . . . . . . . . . . . . 116
Table 104.Pin Mode select register 9 (PINMODE9 - address
0xE002 C064) bit description. . . . . . . . . . . . . 116
Table 105.GPIO pin description . . . . . . . . . . . . . . . . . . . 118
Table 106.GPIO register map (legacy APB accessible
registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 107.GPIO register map (local bus accessible registers
- enhanced GPIO features) . . . . . . . . . . . . . . 119
Table 108.GPIO interrupt register map. . . . . . . . . . . . . . 121
Table 109.GPIO port Direction register (IO0DIR - address
0xE002 8008 and IO1DIR - address
0xE002 8018) bit description . . . . . . . . . . . . . 121
continued >>
UM10211_1
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User manual Rev. 01 — 27 March 2007 585 of 613