UM10211 - Standard ICs

UM10211
Chapter 27: Flash memory programming firmware
Rev. 01 — 27 March 2007
User manual
1. Flash boot loader
2. Features
3. Applications
4. Description
The boot loader controls initial operation after reset, and also provides the means to
accomplish programming of the flash memory. This could be initial programming of a
blank device, erasure and re-programming of a previously programmed device, or
programming of the flash memory by the application program in a running system.
• In-System Programming: In-System programming (ISP) is programming or
reprogramming the on-chip flash memory, using the boot loader software and UART0
serial port. This can be done when the part resides in the end-user board.
• In Application Programming: In-Application (IAP) programming is performing erase
and write operation on the on-chip flash memory, as directed by the end-user
application code.
The flash boot loader provides both In-System and In-Application programming interfaces
for programming the on-chip flash memory.
The flash boot loader code is executed every time the part is powered on or reset. The
loader can execute the ISP command handler or the user application code. A LOW level
after reset at the P2.10 pin is considered as an external hardware request to start the ISP
command handler. Assuming that power supply pins are on their nominal levels when the
rising edge on RESET pin is generated, it may take up to 3 ms before P2.10 is sampled
and the decision on whether to continue with user code or ISP handler is made. If P2.10 is
sampled low and the watchdog overflow flag is set, the external hardware request to start
the ISP command handler is ignored. If there is no request for the ISP command handler
execution (P2.10 is sampled HIGH after reset), a search is made for a valid user program.
If a valid user program is found then the execution control is transferred to it. If a valid user
program is not found, the auto-baud routine is invoked.
Pin P2.10 that is used as hardware request for ISP requires special attention. Since P2.10
is in high impedance mode after reset, it is important that the user provides external
hardware (a pull-up resistor or other device) to put the pin in a defined state. Otherwise
unintended entry into ISP mode may occur.
When ISP mode is entered after a power on reset, the IRC and PLL are used to generate
CCLK of 14.748 MHz. This may not be the case when ISP is invoked by the user
application (see Section 27–9.8 “Reinvoke ISP” on page 532).
UM10211_1
© NXP B.V. 2007. All rights reserved.
User manual Rev. 01 — 27 March 2007 513 of 613