NASA Scientific and Technical Aerospace Reports

This paper had been prepared as a tutorial complement to its companion paper, the ARRAY MATRIX FOR SIGNAL
PROCESSING [I], but could not be presented in the ICASSP-86 framework. Its objective was, and it is so now, to exemplify
some of the adaptations and generalizations of matrix methods stemming from Tait’s ARRAY MATRIX theory [2]. That
theory has since been extended and consolidated as a mathematics of polyxa [3], which can abbet, we believe, the smooth
transition of vector-matrix methods into the array processing era. Through these papers we wish to encourage individual and
collective adoption of what is now called ‘extended’ matrix methods and notation, for communicating work on signal
processing and in system theory. We exemplify this here on rederivation of the remarkable MARPLE algorithm.
Author
Matrices (Mathematics); Matrix Methods; Signal Processing; Systems Analysis
20060002110 Fukui Univ., Japan
On Generalized Feussner’s Principle in a Two-graph
Matsumoto, Tadashi; Hirabayashi, Kimitaka; Nakano, Shigeyoshi; 1987 IEEE International Symposium on Circuits and
Systems, Volume 2; 1987, pp. 507-510; In English; See also 20060002103
Contract(s)/Grant(s): MOE-58550229; MOE-60550245; Copyright; Avail.: Other Sources
The general formulation of the generalized Feussner’s Principle in a two-graph is presented which permits the systematic
and formal classification of all the common trees with respect to an arbitrary subset E(sub s) of edges. The necessary and
sufficient condition for the above class specified by E(sub s) to be an empty set or not is given which is useful for determination
of the optimally classifiable edge-parameters for the finest classification of all the common trees of a two-graph.
Author
Classifications; Graphs (Charts); Trees (Mathematics)
20060002159 California Univ., Berkeley, CA, USA
Architecture Considerations for High Speed Recursive Filtering
Kumar Parhi, Keshab; Wen-Lung, Chen; Messerschmitt, David G.; 1987 IEEE International Symposium on Circuits and
Systems, Volume 2; 1987, pp. 374-377; In English; See also 20060002103
Contract(s)/Grant(s): N00039-86-R-0365; DCI-85-17739; Copyright; Avail.: Other Sources
In this paper, we introduce pipeline interleaving in the incremental block-state structure for pipelined block
implementation of high sampling rate recursive digital filters. We present a new approach to the state update implementation
using a novel decomposition technique. This novel state update implementation, and the incremental output computation
(based on the incremental block-state structure) lead to an efficient implementation of pipelined block recursive digital filters
of (asymptotic) complexity linear in filter order (based on a quasi-diagonal state update matrix) and block size. The complexity
of this implementation as measured by the number of multiplications is asymptotically same as that of non-recursive systems
independent of the implementation methodology. However, for smaller block sizes, bit-level pipelined bit-serial word-parallel
implementation may lead to reduced complexity realization as compared to bit-level pipelined bit-parallel word-parallel
implementation. This comparison is assisted by the concept of an implementable delay operator introduced in this paper.
Author
Architecture (Computers); Digital Filters; Linear Filters; High Speed; IIR Filters
20060002185 Illinois Univ., Urbana-Champaign, IL, USA
Efficient Embedding of Planar Graphs in Linear Time
Tamassia, Roberto; Tollis, Ioannis G.; 1987 IEEE International Symposium on Circuits and Systems, Volume 2; 1987,
pp. 495-498; In English; See also 20060002103
Contract(s)/Grant(s): RSCH-84-06-049-6; Copyright; Avail.: Other Sources
In this paper we consider planar embeddings of n-node planar graphs in the rectilinear grid, where vertices are grid points
and edges are nonintersecting grid paths. We present a new embedding algorithm that runs in linear time. The total number
of bends in the embeddings constructed by our algorithm is very small. Furthermore, the embeddings occupy O(n(sup 2)) area,
which is the best possible in the worst case. Our results are important in the design of VLSI chips. Other applications can be
found in the areas of communication by light or microwave, transportation in space, and automatic graph drawing.
Author
Algorithms; Computational Grids; Very Large Scale Integration; Graph Theory; Edges; Embedding
120