NASA Scientific and Technical Aerospace Reports
NASA Scientific and Technical Aerospace Reports
NASA Scientific and Technical Aerospace Reports
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ealized by means of semi-custom VLSI technique. Example of a switched-capacitor programmable filter is given.<br />
Author<br />
Digital Filters; Switching; Inverted Converters (DC to AC); Capacitors; Integrators<br />
20060002154 Kent Univ., Canterbury, UK<br />
Integrated Circuit Structures for Processing Man-Machine Interaction<br />
Dimond, K. R.; 1987 IEEE International Symposium on Circuits <strong>and</strong> Systems, Volume 2; 1987, pp. 347-350; In English; See<br />
also 20060002103; Copyright; Avail.: Other Sources<br />
Complex electronic equipment is finding increasing use in the factory, office or home. The efficient use of such equipment<br />
is dependent upon the design of the man-machine interface. Since these interfaces are application specific it is vital that<br />
automatic methods are developed to produce custom integrated circuits (i.c.’s) to process the human interaction. This paper<br />
investigates a notation for describing a very wide range of man-machine interaction <strong>and</strong> shows how this specification can be<br />
transformed into custom integrated structures with the minimum of human interaction. A description is given of the operation<br />
of the software tools <strong>and</strong> the steps which are taken to minimise the resulting silicon structure. The technique may be applied<br />
to a wide range of application areas from the user interface of modern complex instruments to improving the programmer<br />
interface of microprocessor system interface components.<br />
Author<br />
Integrated Circuits; Man Machine Systems; Application Specific Integrated Circuits; Microprocessors<br />
20060002158 Washington Univ., Seattle, WA, USA<br />
A Signal Space Interpretation of Neural Nets<br />
Ritchey, J. A.; Atlas, L. E.; Somani, A.; Nguyen, D.; Holt, F.; 1987 IEEE International Symposium on Circuits <strong>and</strong> Systems,<br />
Volume 2; 1987, pp. 370-373; In English; See also 20060002103<br />
Contract(s)/Grant(s): LD2709; Copyright; Avail.: Other Sources<br />
Hopfield neural net processors (NNP) have been shown to be an interesting class of fault tolerant, parallel computers for<br />
pattern recognition. In this paper, we give some limited simulation results that contrast the performance of the Hopfield NNP,<br />
whose T-matrix is in sum-of-outer-products form, <strong>and</strong> the Projection NNP, which uses an orthogonal projection onto the linear<br />
space spanned by the library elements. A Compact NNP is introduced which promises good recall ability with a low density<br />
of neuron interconnections.<br />
Author<br />
Neural Nets; Fault Tolerance; Pattern Recognition; Parallel Computers; Neurons<br />
20060002161 Northeastern Univ., Boston, MA, USA<br />
Efficient Array Processing Structures for Adaptive Quadratic Digital Filters<br />
Lou, Yuang; Nikias, Chrysostomos L.; Venetsanopoulos, Anastasios N.; 1987 IEEE International Symposium on Circuits <strong>and</strong><br />
Systems, Volume 2; 1987, pp. 547-550; In English; See also 20060002103<br />
Contract(s)/Grant(s): NSF ECS-86-01307; Copyright; Avail.: Other Sources<br />
There are many significant applications of nonlinear adaptive digital filters such as the cancellation of echoes <strong>and</strong><br />
intersymbol interference, the equalization of transmission channels, adaptive noise cancellation <strong>and</strong> design of optimal<br />
predictors in communication systems. In this paper, we introduce a class of efficient architectures for adaptive quadratic digital<br />
filters based on the LMS algorithm <strong>and</strong> on rank compressed lower-upper (LU) triangular decomposition method. The<br />
architectures exhibit high parallelism as well as modularity <strong>and</strong> regularity. They are mapped into parallel pipeline <strong>and</strong> systolic<br />
array implementations <strong>and</strong> are evaluated on hardware cost (in bits), <strong>and</strong> data throughput delay.<br />
Author<br />
Digital Filters; Nonlinear Filters; Very Large Scale Integration; Adaptive Filters<br />
20060002162 Illinois Univ., Urbana-Champaign, IL, USA<br />
A Procedure for a Chip Floorplanning<br />
Hsu, Yu-Chin; Kubitz, William J.; 1987 IEEE International Symposium on Circuits <strong>and</strong> Systems, Volume 2; 1987,<br />
pp. 568-571; In English; See also 20060002103; Copyright; Avail.: Other Sources<br />
This paper presents a procedure for chip floorplanning. The system is divided into several subtasks such that one can<br />
evaluate <strong>and</strong> revise the intermediate results <strong>and</strong> incrementally input design decisions. Both an initial placement algorithm <strong>and</strong><br />
a packing algorithm are discussed. In the initial placement algorithm, the area of each module as well as its interconnections<br />
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