NASA Scientific and Technical Aerospace Reports

20060002148 American Telephone and Telegraph Technology Systems, Allentown, PA, USA
The Evolution of Test Heads in High Frequency VLSI Test Systems
Barber, Mark R.; 1987 IEEE International Symposium on Circuits and Systems, Volume 2; 1987, pp. 520-525; In English;
See also 20060002103; Copyright; Avail.: Other Sources
LSI test systems built in the 1970’s were equipped with compact, 60-pin, test heads that presented devices-under-test
(DUT)s with open wires leading to lumped-capacitive loads. Today’s VLSI testers have much larger, 256-pin test heads with
transmission lines leading from the DUT’s to driver-comparator circuits that are sometimes 50 cm away. Reflections within
the transmission lines can cause timing measurement errors as large as 10 ns when testing MOS devices whose output
impedances are not matched to the transmission lines. These errors will occur even though the automatic test equipment is
adjusted to subnanosecond accuracy. From a testing point of view it would be desirable if future sub-micron silicon and
gallium arsenide very high speed IC’s could be designed to drive transmission lines that are terminated with matched resistors
at the comparators.
Author
High Frequencies; Very Large Scale Integration; Systems Engineering; Comparator Circuits; Automatic Test Equipment
20060002149 Ohio Univ., Athens, OH, USA
VLSI Device Characterization for Accurate Delay Measurements Under Transmission Line Effects
Mokari-Bolhassan, M. E.; Kang, S. M.; 1987 IEEE International Symposium on Circuits and Systems, Volume 2; 1987,
pp. 526-529; In English; See also 20060002103
Contract(s)/Grant(s): 85-12-109; Copyright; Avail.: Other Sources
The majority of the new VLSI chips have more than 125 pins, thus making it very difficult to place the tester’s high
impedance comparator circuits close to the contact pads of the device-undertest (DUT). The actual measurement of the signals
form the DUT is performed at the far end of transmission lines 50 cm or more away from the contact pads. This non-ideal
measurement suffers from waveform distortions and errors which are caused by the intrinsic delay of the transmission lines
and also the loading conditions at both ends of the transmission lines. In this paper the non-ideal measurement problem Is
analyzed with mathematical mode]s and analytical results are applied to correct the measurement errors with computer aids.
A new technique is presented to evaluate the true output delay time of the DUT under specified loading conditions using the
measured data from an imperfect measurement set up.
Author
Delay Lines; Transmission Lines; Very Large Scale Integration; Characterization; Mathematical Models
20060002152 Texas A&M Univ., College Station, TX, USA
Generation of Continuous-Time Two Integrator Loop OTA Filter Structures
Sanchez-Sinencio, Edgar; Geiger, Randall L.; Nevarez-Lozano, Horacio; 1987 IEEE International Symposium on Circuits and
Systems, Volume 2; 1987, pp. 325-328; In English; See also 20060002103; Copyright; Avail.: Other Sources
Generation of two integrator loop filter structures using operational Transconductance Amplifier (OTAs) and Capacitors
(TAC) is presented. A direct block diagram approach is employed to generate the TAC filter structures. The basic filter building
blocks consist of a Lossless Integrator, Lossy Integrators and three types of summers. They are implemented using OTAs as
the active components. The resulting TAC 2nd-order filter structures, are orderly generated. The selection of the best structure
depends upon the particular application or design specifications. Programmability of w (sub p 3) Q(sub p) and voltage gain
is considered. The generated TAC biquadratic structures are very suitable for monolithic filters since typically only OTAs and
two capacitors are needed.
Author
Capacitors; Integrators; Operational Amplifiers; Transconductance
20060002153 Canadian Marconi Co. Ltd., Montreal, Quebec, Canada
Digitally Programmable SC-Filters Compatible with Semi-Custom VLSI
Faruque, S. M.; Martens, W.; DeCombe, C.; 1987 IEEE International Symposium on Circuits and Systems, Volume 2; 1987,
pp. 339-341; In English; See also 20060002103
Contract(s)/Grant(s): A4489; Copyright; Avail.: Other Sources
A design technique for programmable analog filters is proposed. The basic building block in this realization is aDtoA
converter whose weighted-current output is directly fed into an integrating capacitor to obtain a programmable integrator.
Analog filters based on this integrator then become digitally programmable, It has the flexibility of digital filters and can be
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