NASA Scientific and Technical Aerospace Reports

are considered and modeled as an unconstrained minimization problem. The area of bounding rectangle is iteratively reduced
by changing the shapes of modules according to their shape constraints in the packing algorithm. A novel feature of the
packing algorithm is that modules are ‘shift back’ to obtain the maximal slack regions. Experimental results show that this
method achieves better area utilization and shorter wiring length than the slicing structure approach.
Author
Iteration; Algorithms; Optimization; Chips (Electronics)
20060002163 Michigan State Univ., East Lansing, MI, USA
An Improved Building Block Model for Placement Using Simulated Annealing
Man-Kuan, Vai; Shanblatt, Michael A.; 1987 IEEE International Symposium on Circuits and Systems, Volume 2; 1987,
pp. 572-575; In English; See also 20060002103; Copyright; Avail.: Other Sources
An improved building block model that guarantees overlap between building blocks will not occur in the simulated
annealing VLSI placement process is presented. In addition, the model reduces the size of the problem space so that a solution
is found more rapidly. Experimental results show that a significant reduction in computation time is achieved over existing
simulated annealing placement programs.
Author
Simulated Annealing; Very Large Scale Integration; Mathematical Models; Algorithms
20060002164 California Univ., Berkeley, CA, USA
Efficient Go/No-Go Testing of Analog Circuits
Milor, Linda; Visvanathan, V.; 1987 IEEE International Symposium on Circuits and Systems, Volume 2; 1987, pp. 414-417;
In English; See also 20060002103; Copyright; Avail.: Other Sources
In order to judge the efficiency of sets of tests and speed up testing of analog-circuits, a circuit-level fault-based approach
to analog testing is presented. Despite the fact that many specifications are bounds on the dynamic behaviour of a circuit, we
suggest that DC testing may be able to detect many faulty circuits and present a systematic approach to DC testing. We then
evaluate the effectiveness of DC testing by applying this methodology to some CMOS analog subnetworks.
Author
Analog Circuits; Dynamic Characteristics; Performance Tests; Fault Tolerance
20060002165 Princeton Univ., NJ, USA
Variable Step Size Methods for the LMS Adaptive Algorithm
Evans, Joseph B.; Liu, Bede; 1987 IEEE International Symposium on Circuits and Systems, Volume 2; 1987, pp. 422-425;
In English; See also 20060002103
Contract(s)/Grant(s): ECS 83-17777; Copyright; Avail.: Other Sources
Variable step size (VS) algorithms present an attractive method of overcoming the slow convergence rate problems of the
least mean square (LMS) adaptive algorithm, with minimal added cost in complexity. Simulation and theoretical results are
presented for two types of VS algorithms. Also included are results demonstrating the performance of these algorithms when
a power-of-two quantizer is used. Implementation considerations are briefly discussed.
Author
Algorithms; Convergence; Least Squares Method; Mean Square Values
20060002166 Ottawa Univ., Ontario, Canada
The LMS Algorithm Applied to High Speed Adaptive Digital Signal Processing
Savov, Emil; Steenaart, Willem; 1987 IEEE International Symposium on Circuits and Systems, Volume 2; 1987, pp. 430-433;
In English; See also 20060002103
Contract(s)/Grant(s): NSERC-A8572; Copyright; Avail.: Other Sources
The topics discussed in this paper are related to the use of VLSI (Very Large Scale Integration) components in high-speed
adaptive digital signal processing and more specifically concerning the LMS (Least Mean Square) algorithm. The problem of
sequential coefficient access is addressed. Some alternative architectures are proposed which are shown to be efficient and
suitable for VLSI-based implementations. A modified version of the LMS algorithm is also introduced which uses a filtered
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