NASA Scientific and Technical Aerospace Reports

architectural features and speed with the register file to do high bandwidth fast Fourier transforms in a variety of different
configurations.
Author
Accumulators; Bipolarity; Fabrication; High Speed
20060001598 Edinburgh Univ., UK
Techniques to Increase the Computational Throughput of Bit-Serial Architectures
Smith, S. G.; McGregor, M. S.; Denyer, P. B.; IEEE International Conference on Acoustics, Speech, and Signal Processing
(ICASSP ‘87); Volume 1; 1987, pp. 13.18.1-13.18.4; In English; See also 20060001583; Copyright; Avail.: Other Sources
Three architectural techniques are reported, which accelerate bit-serial computation without compromising its favourable
advantages. In essence these techniques rely on multi-wire representations of serial data - a step towards bit-parallelism.
Interfacing techniques are developed to support the existence of domains of different throughput within a system, thereby
enhancing the range of bandwidth-matching techniques available to the systems designer. These techniques also realise the
potential to mix processing wordlengths within a serial-data system.
Author
Computation; Data Systems; Architecture (Computers)
20060001641 Motorola, Inc., Austin, TX, USA
A Split Control Store VLSI for 32 Kbps ADPCM Transcoding
Bonet, Luis; Williams, Tim A.; IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP ‘87);
Volume 1; 1987, pp. 511-514; In English; See also 20060001583; Copyright; Avail.: Other Sources
This paper describes the architecture used in a 16 pin CMOS VLSI Digital Signal Processor which was designed by the
authors to perform both ANSI and CCITT versions of the ADPCM standard. The part is designed to run from a 20 MHz clock
source with an instruction cycle time of 100 ns. This design is a good example of the power of application specific DSP designs
to reduce the cost of implementing stable algorithms.
Author
Very Large Scale Integration; Digital Systems; Signal Processing; Signal Analyzers
20060001645 Ecole Nationale Superieure des Telecommunications, Paris, France
An Optimized VLSI Architecture for a Multiformat Discrete Cosine Transform
Demassieux, Nicolas; Concordel, Gilles; Durandeau, Jean-Pierre; Jutand, Francis; IEEE International Conference on
Acoustics, Speech, and Signal Processing (ICASSP ‘87); Volume 1; 1987, pp. 13.19.1-13.19.4; In English; See also
20060001583; Copyright; Avail.: Other Sources
This communication presents an optimized architecture providing the computation power and the versatility that are
required for the real-time processing of various blocks format (from 4x4 to 16x16) and for direct/inverse Discrete Cosine
Transform. To achieve a realistic single chip implementation, different architectures have been compared. Circuits based on
the most efficient architecture will be used for a real-time coder/decoder of color images.
Author
Very Large Scale Integration; Architecture (Computers); Optimization; Computation
20060001686 Nippon Telegraph and Telephone Public Corp., Atsugi, Japan
A Flexible Linear Array Oriented VLSI Processor for Continuous Speech Recognition
Takahashi, Jun-ichi; Kimura, Takashi; IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP
‘87); Volume 1; 1987, pp. 499-502; In English; See also 20060001583; Copyright; Avail.: Other Sources
A PE (Processing Element) LSI for a DTW (Dynamic Time Warping) linear array processor has been designed. In
designing this LSI, major effort has been focused on achieving regular data-flow among adjacent PEs maintaining pipelined
operation in the array. A three data channel structure, a triple buffer structure and sophisticated control schemes make it
possible for the designed LSI to carry out ESA Multiple Instruction and Multiple Data streams} and continuous pipelined
DTW processing in sync with regular pattern input. Due to the high speed real time operation, and the versatile function of
this PE-LSI, a high performance linear array processor can be constructed using a small number of PEs. The high speed
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