NASA Scientific and Technical Aerospace Reports

operation of LSI is pursuited to achieve real time processing. Continuous speech recognition with an approximate vocabulary
of 1000 words can be achieved using only 20 to 30 of these PE-LSIs.
Author
Linear Arrays; Very Large Scale Integration; Speech Recognition
20060001689 Florida Univ., FL, USA
A Reconfigurable Binary/RNS/LNS Architecture for DSP
Taylor, Fred J.; IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP ‘87); Volume 1; 1987,
pp. 503-506; In English; See also 20060001583; Copyright; Avail.: Other Sources
An integrated digital signal processing machine will accept data from a plethera of sensors and/or subsystems which may
be running at different speeds and with different precision/dynamic range metrics. Data would be manipulated using a set of
algorithms which perform a variety of filtering or transform tasks. The design of such a machine considered in this paper,
integrates recent advancements in mesh array synthesis with processor technology. The result is a high-throughput GIPS class
DSP machine capable of responding to a wide mix of system and user defined DSP problems.
Author
Binary Codes; Signal Processing; Architecture (Computers); Digital Systems
20060001692 Motorola, Inc., Schaumburg, IL, USA
A Cascadable Adaptive FIR Filter VLSI IC
Borth, David E.; Gerson, Ira A.; Haug, John R.; IEEE International Conference on Acoustics, Speech, and Signal Processing
(ICASSP ‘87); Volume 1; 1987, pp. 515-518; In English; See also 20060001583; Copyright; Avail.: Other Sources
This paper describes the architecture and features of the Motorola DSP56200, an algorithm-specific cascadable digital
signal processing peripheral designed to perform the computationally intensive tasks associated with FIR and adaptive FIR
digital filtering applications. The DSP56200 is implemented in high performance, low power 1.51 micron HCMOS technology
and is available in a 28 pin DIP package. The on-chip computation unit includes a 97.5 ns 24x16-bit multiplier with a 40-bit
accumulator, a 256x24-bit coefficient RAM,and a 256x16-bit data RAM. Three modes of operation allow the part to be used
as a single FIR filter, a dual FIR filter, or a single adaptive FIR filter, with up to 256 taps/chip. In the adaptive FIR filter mode,
the part performs the FIR filtering and LMS coefficient update operations for a single tap in 195 ns, permitting use of the part
as a 19kHz sampling rate. 256 tap adaptive FIR filter, Programmable DC tan coefficient leakage and adaption coefficient
parameters in the adaptive FIR mode allow the DSP56200 to be used in a wide variety of adaptive FIR filtering applications.
The performance of the part in an echo canceller configuration will be presented. Typical applications of the part will also be
described.
Author
Cascade Control; Architecture (Computers); Signal Processing; Chips; Adaptive Filters
20060001819 Duke Univ., Durham, NC USA
Load Latency Tolerance in Dynamically Scheduled Processors
Srinivasan, Srikanth T.; Lebeck, Alvin R.; Jan. 1, 2005; 13 pp.; In English
Contract(s)/Grant(s): DABT63-98-1-0001; CDA-97-2637
Report No.(s): AD-A440304; No Copyright; Avail.: Defense Technical Information Center (DTIC)
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To
determine the latency tolerance of each memory load operation, our simulations use flexible load completion policies instead
of a fixed memory hierarchy that dictates the latency. Although our policies delay load completion as long as possible, they
produce performance (instructions committed per cycle (IPC)) comparable to an ideal memory system where all loads
complete in one cycle. Our measurements reveal that to produce IPC values within 8% of the ideal memory system, between
1% and 62% of loads need to be satisfied within a single cycle and that up to 84% can be satisfied in as many as 32 cycles,
depending on the benchmark and processor configuration. Load latency tolerance is largely determined by whether an
unpredictable branch is in the load s data dependence graph and the depth of the dependence graph. Our results also show that
up to 36% of all loads miss in the level one cache yet have latency demands lower than second level cache access times. We
also show that up to 37% of loads hit in the level one cache even though they possess enough latency tolerance to be satisfied
by lower levels of the memory hierarchy.
DTIC
Computer Storage Devices; Loads (Forces)
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