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NASA Scientific and Technical Aerospace Reports

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these ‘process certificates’ are the first type of certification that will be discussed here. The second type of software certification<br />

often mentioned refers to the licensing of software engineering professionals; this is still referred to as software certification<br />

but should more appropriately be referred to as ‘professional licensing.’ The third <strong>and</strong> most important, but most difficult, claim<br />

that a certificate can make is to discuss how the software will behave in use. This is referred to as ‘product certification’ <strong>and</strong><br />

that will be our focus here.<br />

Derived from text<br />

Certification; Software Engineering; Computer Programming; Controllers; Embedding; Interoperability; Protocol<br />

(Computers); Systems Engineering<br />

20060001599 California Univ., USA<br />

Linear Feature Extraction Based on an AR Model Edge Detector<br />

Yi-Tong, Zhou; Chellappa, Rama; IEEE International Conference on Acoustics, Speech, <strong>and</strong> Signal Processing (ICASSP ‘87);<br />

Volume 1; 1987, pp. 555-558; In English; See also 20060001583<br />

Contract(s)/Grant(s): F-49622-85-C-0071; Copyright; Avail.: Other Sources<br />

Extraction of linear features is an important task in many image underst<strong>and</strong>ing <strong>and</strong> computer vision systems. In this paper,<br />

we describe a linear feature extractor which operates on the edge pixels detected by a space varying2-Dautoregressive (AR)<br />

model. The sequence of steps for extraction of linear segments consists of tracing the edge points, linking <strong>and</strong> fitting with lines.<br />

The heuristics used in tracing <strong>and</strong> linking steps are specific to the characteristics of the AR model based edge detector. The<br />

performance of the linear feature extractor is illustrated using real images.<br />

Author<br />

Two Dimensional Models; Extraction; Heuristic Methods; Linear Programming<br />

20060001642 Bell Telephone Labs., Inc., Murray Hill, NJ, USA<br />

The Graph Search Machine (GSM): A Programmable Processor for Connected Word Speech Recognition <strong>and</strong> Other<br />

Applications<br />

Glinski, Stephen; Lalumia, T. Mariano; Cassiday, Dan; Koh, Taiho; Gerveshi, Christine; Wilson, Gene; Kumar, Jit; IEEE<br />

International Conference on Acoustics, Speech, <strong>and</strong> Signal Processing (ICASSP ‘87); Volume 1; 1987, pp. 13.12.1 - 13.12.4;<br />

In English; See also 20060001583; Copyright; Avail.: Other Sources<br />

A programmable VLSI processor is described for efficiently computing a variety of kernel operations for speech<br />

recognition. These operations include dynamic programming for isolated <strong>and</strong> connected word recognition using both the<br />

template matching approach <strong>and</strong> the Hidden Markov Model (HMM) approach, dynamic programming for natural language<br />

models, <strong>and</strong> metric computations for vector quantization <strong>and</strong> distance measurement. As well as being able to efficiently<br />

compute a wide class of speech processing operations, the architecture is useful in other areas such as image processing.<br />

Working chips have been produced using 1.5 micron CMOS design rules that combine beth custom <strong>and</strong> st<strong>and</strong>ard cell<br />

approaches.<br />

Author<br />

Dynamic Programming; Image Processing; Natural Language (Computers); Programming Languages<br />

20060001644 Edinburgh Univ., UK<br />

Serial/Parallel Architectures for Area-Efficient Vector Multiplication<br />

Smith, S. G.; Denyer, P. B.; IEEE International Conference on Acoustics, Speech, <strong>and</strong> Signal Processing (ICASSP ‘87);<br />

Volume 1; 1987, pp. 13.17.1 - 13.17.4; In English; See also 20060001583; Copyright; Avail.: Other Sources<br />

The use of st<strong>and</strong>ard-part multiply/accumulators in digital signal processing is often in the computation of vector products.<br />

In the realm of custom VLSI, direct computation of vector products can result in area savings over classical multiply/<br />

accumulate methods. A methodology is presented for composition of VLSI architectures for direct vector multiplication, based<br />

on three fundamental computational elements. These are register, data selecter, <strong>and</strong> carry-save add-shift (CSAS) computer. The<br />

CSAS computer is a linear array of gated carry-save adders which performs shifting accumulation of partial results. Two’s<br />

complement serial/parallel carry-save accumulation provides performance, while the use of symmetric-coded distributed<br />

arithmetic eliminates redundant computation to effect area-savings.<br />

Author<br />

Series (Mathematics); Parallel Processing (Computers); Architecture (Computers); Vector Processing (Computers)<br />

129

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