NASA Scientific and Technical Aerospace Reports
NASA Scientific and Technical Aerospace Reports
NASA Scientific and Technical Aerospace Reports
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20060002120 Audesyn, Inc., Edmonton, Alberta, Canada<br />
Loop Winding-A Data Flow Approach to Functional Pipelining<br />
Girczyc, E. F.; 1987 IEEE International Symposium on Circuits <strong>and</strong> Systems, Volume 2; 1987, pp. 382-385; In English; See<br />
also 20060002103; Copyright; Avail.: Other Sources<br />
This paper discusses loop winding as a technique for increasing the data throughput of a repeated algorithm (loop). Loop<br />
winding allows a conventional circuit synthesis algorithm to be used to generate pipelined circuits by modifying the data flow<br />
graph of the algorithm in a preprocessing phase. Loop winding partitions each loop iteration according to path length <strong>and</strong> then<br />
winds these in parallel to form a shorter loop executing at a higher frequency. This achieves a functional pipeline as operations<br />
from several iterations of the loop are executed in parallel without forcing the algorithm onto a pipeline structure. The removal<br />
of the pipeline structure achieves better sharing of resources because of the removal of the concept of ‘stages’. In addition to<br />
increasing throughput, loop winding can also be used to decrease circuit size by increasing the flexibility of operation<br />
assignment, <strong>and</strong> to decrease the latency of an algorithm by pipelining nested, finite length loops.<br />
Author<br />
Loops; Pipelining (Computers); Information Flow; Graphs (Charts); Circuits; Algorithms<br />
20060002121 Colorado Univ., Boulder, CO, USA<br />
Functional Reconfiguration in Fixed-Size VLSl Arrays<br />
Lombardi, F.; Sciuto, D.; Stefanelli, R.; 1987 IEEE International Symposium on Circuits <strong>and</strong> Systems, Volume 2; 1987,<br />
pp. 386-389; In English; See also 20060002103; Copyright; Avail.: Other Sources<br />
This paper presents different methods for reconfiguring a fixed-size array into an array of arbitrary rectangular shape. This<br />
type of reconfiguration is referred to as functional reconfiguration as it maps processing functionalities (given by an algorithm)<br />
into an array of different dimensions. It is proved that overhead for switching <strong>and</strong> routing is minimal.<br />
Author<br />
Algorithms; Switching; Very Large Scale Integration; Arrays<br />
20060002125 Rice Univ., Houston, TX, USA<br />
A New Nonlinear Technique for IC Fixed Tolerance Design Centering Based on a Modified Simplex Method<br />
Pham, Trung T.; deFigueiredo, Rui J. P.; 1987 IEEE International Symposium on Circuits <strong>and</strong> Systems, Volume 2; 1987,<br />
pp. 406-409; In English; See also 20060002103<br />
Contract(s)/Grant(s): N00014-85-K0152; Copyright; Avail.: Other Sources<br />
In this paper, we present a new technique for design centering, in integrated circuit design, based on a modification of<br />
the simplex method. Specifically, we focus attention on the determination of the worst case functions in the fixed tolerance<br />
problem. The technique presented by us solves a pseudo linear programming problem with a nonlinear objective function <strong>and</strong><br />
linear constraints.<br />
Author<br />
Integrated Circuits; Linear Programming; Simplex Method; Algorithms<br />
20060002126 Notre Dame Univ., IN, USA<br />
Fault Diagnosis of Piecewise-Linear Circuits<br />
Huang, Qiu; Liu, Roey-wen; 1987 IEEE International Symposium on Circuits <strong>and</strong> Systems, Volume 2; 1987, pp. 418-421;<br />
In English; See also 20060002103; Copyright; Avail.: Other Sources<br />
The problem of K-fault diagnosis problem of piecewise-linear systems are Investigated. A fault-diagnosis equation Is<br />
derived. Based on it, a linear method is hence proposed. A piecewise-linear circuit is used as an illustrative example. f(x) =<br />
A(x)x - b(x) (2.2) where A(x) eRnxn<strong>and</strong>b(x)eRn,whose elements are functions of x. Furthermore, let<br />
Author<br />
Fault Detection; Error Analysis; Linear Circuits; Linear Systems<br />
20060002127 Massachusetts Inst. of Tech., Lexington, MA, USA<br />
A Phase-Plane Approach to the Compensation of High-Speed Analog-to-Digital Converters<br />
Rebold, T. A.; Irons, F. H.; 1987 IEEE International Symposium on Circuits <strong>and</strong> Systems, Volume 2; 1987, pp. 455-458; In<br />
English; See also 20060002103; Copyright; Avail.: Other Sources<br />
This paper outlines a practical method for decreasing the harmonic distortion of high-speed (1 to 100 MHz)<br />
analog-to-digital converters (ADCs), making them more suitable for Fast Fourier Transform (FFT) spectral analysis<br />
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