Callister - An introduction - 8th edition

750 • Chapter 18 / Electrical Properties
Voltage, V
Reverse Forward
0
–V 0
Figure 18.23 (a) Voltage versus time for
the input to a p–n rectifying junction.
(b) Current versus time, showing
rectification of voltage in (a) by a p–n
rectifying junction having the
voltage–current characteristics shown in
Figure 18.22.
+V 0
(a)
Time
I F
Current, I
Reverse Forward
0
I R
Time
(b)
The rectification process in terms of input voltage and output current is
demonstrated in Figure 18.23. Whereas voltage varies sinusoidally with time
(Figure 18.23a), maximum current flow for reverse bias voltage I R is extremely
small in comparison to that for forward bias I F (Figure 18.23b). Furthermore,
correspondence between I F and I R and the imposed maximum voltage (;
V 0 ) is
noted in Figure 18.22.
At high reverse bias voltages, sometimes on the order of several hundred volts,
large numbers of charge carriers (electrons and holes) are generated. This gives rise
to a very abrupt increase in current, a phenomenon known as breakdown, also shown
in Figure 18.22, and discussed in more detail in Section 18.22.
junction transistor
MOSFET
The Transistor
Transistors, which are extremely important semiconducting devices in today’s microelectronic
circuitry, are capable of two primary types of function. First, they can
perform the same operation as their vacuum tube precursor, the triode; that is, they
can amplify an electrical signal. In addition, they serve as switching devices in computers
for the processing and storage of information. The two major types are the
junction (or bimodal) transistor and the metal-oxide-semiconductor field-effect transistor
(abbreviated as MOSFET).
Junction Transistors
The junction transistor is composed of two p–n junctions arranged back to back in
either the n–p–n or the p–n–p configuration; the latter variety is discussed here.
Figure 18.24 is a schematic representation of a p–n–p junction transistor along with
its attendant circuitry. A very thin n-type base region is sandwiched in between
p-type emitter and collector regions. The circuit that includes the emitter–base junction
(junction 1) is forward biased, whereas a reverse bias voltage is applied across
the base–collector junction (junction 2).