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Callister - An introduction - 8th edition

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18.15 Semiconductor Devices • 751<br />

Figure 18.24<br />

Schematic diagram<br />

of a p–n–p junction<br />

transistor and its<br />

associated circuitry,<br />

including input and<br />

output voltage–time<br />

characteristics<br />

showing voltage<br />

amplification.<br />

(Adapted from A. G.<br />

Guy, Essentials of<br />

Materials Science,<br />

McGraw-Hill Book<br />

Company, New York,<br />

1976.)<br />

Forward-biasing voltage<br />

0.1<br />

Input<br />

voltage<br />

(mV)<br />

+<br />

–<br />

Time<br />

Junction 1<br />

Input<br />

voltage<br />

Emitter<br />

p<br />

Base<br />

n<br />

10<br />

Output<br />

voltage<br />

(mV)<br />

Junction 2<br />

Collector<br />

p<br />

Load<br />

Output<br />

voltage<br />

Time<br />

–<br />

+<br />

Reverse-biasing voltage<br />

Figure 18.25 illustrates the mechanics of operation in terms of the motion of<br />

charge carriers. Because the emitter is p-type and junction 1 is forward biased,<br />

large numbers of holes enter the base region. These injected holes are minority<br />

carriers in the n-type base, and some will combine with the majority electrons.<br />

However, if the base is extremely narrow and the semiconducting materials have<br />

been properly prepared, most of these holes will be swept through the base without<br />

recombination, then across junction 2 and into the p-type collector. The holes<br />

now become a part of the emitter–collector circuit. A small increase in input voltage<br />

within the emitter–base circuit produces a large increase in current across<br />

junction 2. This large increase in collector current is also reflected by a large<br />

increase in voltage across the load resistor, which is also shown in the circuit<br />

(Figure 18.24). Thus, a voltage signal that passes through a junction transistor experiences<br />

amplification; this effect is also illustrated in Figure 18.24 by the two<br />

voltage–time plots.<br />

Similar reasoning applies to the operation of an n–p–n transistor, except that<br />

electrons instead of holes are injected across the base and into the collector.<br />

p-Type n-Type p-Type<br />

+ + +<br />

+ +<br />

+ +<br />

<br />

+ + +<br />

+<br />

+<br />

+<br />

+<br />

+ + <br />

+ +<br />

(a)<br />

+<br />

+<br />

Figure 18.25 For a junction transistor (p–n–p<br />

type), the distributions and directions of<br />

electron and hole motion (a) when no<br />

potential is applied and (b) with appropriate<br />

bias for voltage amplification.<br />

Junction 1 Junction 2<br />

Emitter Base Collector<br />

+ +<br />

+ +<br />

+<br />

+<br />

<br />

+<br />

+<br />

+ + + +<br />

+ + –<br />

<br />

+<br />

+ +<br />

+ + + +<br />

–<br />

(b)<br />

+

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