VHDL Kurzbeschreibung

component instantiation statementlabel : component name[generic map (map)][portmap (signals)];entity ENT isbegin.......end ENT;architecture ARC of ENT isbegin.......end ARC;B: blockbegin.......package PKG isend PKG;P: processbegin.......package body PKG isend PKG;configuration CONF of ENT isend CONF;procedure P (...) isbegin.......end block B;end process P;end P;114