VHDL Kurzbeschreibung

A.9 Reservierte Bezeichnerabs element label package thenaccess else library port toafter elsif linkage postponed transportalias end literal private typeall entity loop procedureallow exit process unaffectedand map pure unitsarchitecture file mod untilarray for range useassert function nand recordattribute new register variablegenerate next rejectbegin generic nor rem waitblock group not report whenbody guarded null return whilebuffer rol withbus if of rorimpure on xnorcase in open select xorcomponent initial or severityconfiguration inout others signalconstant is out sharedsladisconnectslldowntosrasrlsubtype118