VHDL Kurzbeschreibung

A.3 Deklarationengeneric declarationgeneric (identier list : type [:= expression];fidentier list : type [:= expression];g );entity ENT isbegin.......=package PKG ispackage body PKG isend ENT;end PKG;end PKG;architecture ARC of ENT isconfiguration CONF of ENT isbegin.......end ARC;end CONF;B: blockP: processprocedure P (...) isbegin.......begin.......begin.......end block B;end process P;end P;79