VHDL Kurzbeschreibung

package declarationpackage identier ispackage declarative partend [identier];entity ENT ispackage PKG ispackage body PKG isbegin.......end ENT;end PKG;end PKG;architecture ARC of ENT isconfiguration CONF of ENT isbegin.......end ARC;end CONF;B: blockP: processprocedure P (...) isbegin.......begin.......begin.......end block B;end process P;end P;76