VHDL Kurzbeschreibung

le declarationfile identier : type is [mode] logical name;entity ENT isbegin.......end ENT;architecture ARC of ENT isbegin.......end ARC;B: blockbegin.......=package PKG isend PKG;beginP: process ?.......B ZBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBNZZZZZZZZZZ~package body PKG isend PKG;configuration CONF of ENT isend CONF;procedure P (...) isbegin.......end block B;end process P;end P;86