Product Description XI/ON - Eaton Automation

XI/ON: Gateways for Modbus TCP 9 Appendix
Control bit Explanations
SET_DO1 If CTRL_DO1 = 1 and the physical output DO1 is set
to indicate the value SET_DO1, DO1 can be set and
reset directly with SET_DO1.
DO1 can be set for this function via the process
output (MODE_DO1 = 00 and LOAD_DO_PARAM
“0“ → “1“). The output DO2 can also be set before
commissioning via the separate parameter data.
The default setting for DO1 is to display the value of
SET_DO1.
RES_STS “0“ → “1“ Initiate resetting of status bits. Status bits
STS_ND, STS_UFLW, STS_OFLW, STS_CMP2,
STS_CMP1, STS_SYN (process input) are reset.
Bit RES_STS_A = 1 (process input) acknowledges
that the reset command has been received.
RES_STS can now be reset to 0.
CTRL_SYN Release synchronization
1: “0“ → “1“ (rising edge) at the physical DI input
enables the counter value to be set (synchronized)
once/periodically to the load value.
SW_GATE “0“ → “1“: Counting is started (release).
“1“ → “0“: Counting is stopped.
The starting and stopping of the counting operation
with a data bit is implemented with a so-called “SW
gate”. The HW gate is also provided in addition for
stopping and starting the counting operation via the
DI hardware input. If this function is configured a
positive signal must be present at this input in order
to activate the SW gate (AND logic operation).
LOAD_
DO_PARAM
Parameter definition of the DO1 physical output and
the virtualA DO2 output
“0“ → “1“: DO1 and DO2 can indicate the status of
data bit SET_DO1 and SET_DO2 or comparison
results. The latest telegram (MODE_DO1 and
MODE_DO2) indicates the function required for DO1
and DO2.
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