PDP11 PeripheralsHbk 1972 - Trailing-Edge

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PART I Chapter 4 Display Terminals Several display options are available from Digital Equipment Corporation, in· cluding a storage display unit (VTOlA), an oscilloscope (VROlA), a point plot dis· play (VR14), and an alphanumeric display terminal (VT05). Each of the units must be interfaced to the PDP· 11 UNIBUS via an interface and control subsystem. General characteristics and specifications of the various displays are included in this chapter. For information on the controls and programming see Chapter 9 for AAll·D control and Chapter 2 for the KLll control. VTO lA Storage Display 55
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CONTENTS PART I Chapter 1· Program
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viii
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Chapter 8 - COMMUNICATIONS OPTIONS
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6 5-4 3-1 o Interrupt Enable Memory
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PART I Chapter 2 Basic I/O Terminal
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2.2.3 Programming Examples Reading
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Model Type Power Descri ption L T33
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Punch Interrupt Service This interr
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LPII HIGH SPEED LINE PRINTER 19
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BIT 15 14 13 12 11 10 9 8 7 6 NAME
Page 76: LA30-DECwriter 29
Page 82: Ribbon: Code: Temperature: Humidity
Page 88: Figure 3"2 - DECtape Block Arrangem
Page 98: 3-1 Function Bits o DO' Word Count
Page 104: Density: Data Capacity: Tape Motion
Page 108: TU 10 MAGTAPE UNIT 3.2.2 Operation
Page 118: 10 End of Tape (EaT) 9 Record Lengt
Page 122: When the MTBRC is used in a space f
Page 132: 4.4 POINT PLOT DISPLAY VR14 The VR1
Page 136: 4.5.1 Specifications Screen Size: C
Page 140: DEC-links usage may be defined enti
Page 146: Real-time look ahead is provided by
Page 162: Average Access Time: Maximum Access
Page 168: BIT NAME 15 Error (ERR) 14 Freeze (
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5.3.5 Specifications Disks: Tracks:
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DECPACK DISK CARTRIDGE SYSTEM 82
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11 Inhibit Inc. (INH SA) Setting th
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those functions. such as CONTROL RE
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BIT 15 NAME Error 14-8 Unused 7 Don
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6.2.2 Interrupt During an interrupt
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The switches do not allow two proce
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7.2.3 Fail-Soft Operation The bus s
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BIT *15 14 13 *12 *11 * 10 9 NAME T
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108
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ety of asynchronous terminals or to
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Receiver Buffer Register (RBUF) Tra
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A Detect Answer option is used. The
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tain an interrupt. It is cleared by
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2. Sync characters will be treated
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10-8 Bits Per Character 7 Receive D
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Modem Compatibility (Typical) Type
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only for use with the DC08CS distri
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memory used. For the MM'l1-F 950 na
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5-4 Memory Extension 3 Not Used 2 M
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Control Signals: Physical: Environm
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D. Telegraph Line Interfaces DEC NO
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PART I Chapter 9 Data Acquisition a
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9.3.3 Specifcations For D/ A Conver
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9.4.7 Specifications Modes of Opera
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2 UNIBUS AND INTERFACING 171
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PART II Introduction ..............
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PART II INTRODUCTION This section d
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Interrupt Requests Devices that gai
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Lines A specify a unique 16-bit wor
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a. Master sets C =00 for DATI or C=
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a. If immediate interrupt operation
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The bus master places address, cont
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TIME (ns) o 150 225 300 375 450 525
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200
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+5V TYPICAL UNIBUS DRIVER +5V TYPIC
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Figure 2-4 UNIBUS Jumper Module M92
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Table 2-3 Gating Control Signals Mo
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Figure 2-17 State Diagram of Master
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2.2.6 M795 Word Count and Bus· Add
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Table 2·6 M795 Output Signals Asse
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Signal Name BUS C ADRS TO BUS ADRS
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2.4 PDP·ll INTERFACE HARDWARE The
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2.4.2.5 External Device Cables-An e
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Signal levels used in the interface
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3.3.2 DRll-A Implementation A conve
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I\) O'l o READY (1) H START CONVERS
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nel and low COY) for a transfer fro
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5 through 1 of the UNIBUS-to-UNIBUS
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ation and each successive cycle of
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Second, the DRDB functions as a 16
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260 264 270 USER RESERVED 274 USER
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777410 RKBA 777406 RKWC 777404 RKCS
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772546 772544 772542 772540 772536
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770070 LATENCY TESTER 770056 TO 770
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TABLE B-2 UNIBUS PIN ASSIGNMENTS (B
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292
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RS64 Disk .........................
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