PDP11 PeripheralsHbk 1972 - Trailing-Edge

BIT
15
14
13
12
11
10
9
8
7
NAME
Special Condition
Data Error
Address Error
Write Lock
Non-Existent Disk
Write Check Error
Inhibit CA Increment
Abort
Ready
DESCRI PTION
Set to indicate that controller sensed an
error condition. The exact error causing
this bit to set can be found in bits 10-14 of
this register and RCER. This bit is read
only.
Set to indicate that controller sensed a
data error. Data error may be due to sync
or cyclic redundancy check (CRC). The exact
error can be found in RCER. This bit is
read only and initialized to zero.
Set to indicate that controller sensed an
address parity or sync error. The exact error
can be found in RCER. This bit is read
only and initialized to zero.
Set to indicate that a write attempt was
made on a write-protected area of the
disk. This bit is read only and initialized to
zero.
Set to indicate that disk address register
(RCDA) is pointing to a non-existent unit
or the disk unit number in RCDA has overflowed.
Note that this bit will be "l"only
when the word count registerdid not overflow
so that last sector of the last disk unit
can be operated on without getting an error
status. This bit is read only and initialized
to zero.
Set if data read from the disk does not
compare with the data on the bus during a
write check function. Incrementation of
RCCA and RCWC are inhibited as soon as
failure occurs. However, controller reads
the whole block (32 words) for cyclic redundancy
check (CRC). This bit is read only
and initialized to zero.
If declared as "l,"data transfers with the
UNIBUS will be performed without incrementing
RCCA. This bit is read/write
and initialized to zero.
If declared as "l,"any operation in progress
is aborted. This bit is write only and
initialized to zero.
Controller sets this bit to indicate completion
(or abortion) of an operation and
is ready for the next operation. This bit is
read only and initialized to "1."
69