PDP11 PeripheralsHbk 1972 - Trailing-Edge

ation and each successive cycle of operation is initiated by a signal from the device.
In this example, the device is an ADC similar to the ADC described in
Paragraph 3.3. The rate at which successive conversion cycles are performed is
not defined in this example. However, the rate can be controled by an external
clock, so that the clock frequency determines the sampling rate.
A timing diagram is shown in Figure 3-17. The signal that starts a cycle of interface
operation is CONVERSION COMPLETE H. This signal is generated by the
ADC after it has completed conversion of the analog input to a digital value, and
that value is available as a data output from the ADC. The CONVERSION COM­
PLETE signal sets the REQUEST BUS flip-flop which causes the M7820 Master
Control A module to gain control of the UNIBUS by means of an NPR request.
The MASTER A L signal triggers START on the M796 module and, since CYCLE
CONTROL is clear, a DATIP bus cycle is performed. The ADRS TO BUS H signal is
used to gate an address on to the address bus. This address is formed by data
from the ADC (least significant portion of the address) and the field select bits
(most significant portion of the address). After a delay, BUS MSYN L is asserted.
When the slave (usually memory) responds with data and a BUS SSYN L signal,
DATA WAIT L is triggered to allow for deskewing of the data. The trailing edge of
DATA WAIT triggers the DATA STROBE one-shot. The DATA STROBE signal loads
the data present on BUS 0< 15:00> into the interface cou'nter register. When
DATA STROBE times out, DATA ACCEPTED is asserted, negating BUS MSYN, and
firing the COUNT PULSE and COUNT DELAY one-shots. COUNT PULSE is set for
the worst case ripple time of the counter.
When the COU NT DELAY is complete and BUS SSYN L is negated by the previous
DATIP bus cycle, START is again asserted. Since CYCLE CONTROL is now set (set
by END CYCLE of the previous DATIP), a DATO bus cycle is performed. The DATA
TO BUS H signal is asserted and gates the contents of the incremented counter to
the bus data lines.
When the DATO cycle is complete, END CYCLE and CYCLE CONTROL set are AN­
Oed to clear the REQUEST BUS flip-flop, which causes the M7820 module to drop
BUS BBSY L, thereby releasing control of the bus.
3.9_2 Optional Arrangements
The timing chain of DATA WAIT, DATA STROBE, COUNT PULSE, and COUNT DE­
LAY is designed for the case where count time is significant and the counter is
loaded and incremented by a level rather than a transition.
Other logic may be used dependent upon the type and speed of the counter employed
in the interface.
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