PDP11 PeripheralsHbk 1972 - Trailing-Edge

3.10.2 Software Interface
The following presents a detailed description of the four DR11-B registers. These
registers are assigned bus addresses and can be read or loaded (with the exception
noted) using any instruction that refers to their address_ "IN IT" refers to
the initialization signal produced on power up, power down, by the RESET instruction,
or by the start switch on the console. "R/W" stands for read/write. Note
that the INIT signal is held asserted internal to the DRll-B whenever an interlock
error occurs (M968 test board neither in slots AB02 for normal operation nor
CD04 for maintenance mode).
Status and Command Register (DRST)
The DRST is used to give commands to the user device and to provide status indicators
of the DR11·B control and the user device.
BIT
15 Error
NAME MEANING AND OPERATION
Indicates an error condition: either NEX
(BIT 14), ATTN (BIT 13), interlock error
(test board is neither in slots AB02 nor
CD04), or bus address overflow
(BAOF:DRBA incremented from all l's to
all O's). Sets READY (BIT 7) and causes interrupt
if IE (BIT 6) is set. ERROR is
cleared by removing ail four possible error
conditions: interlock error is removed by
inserting test board in CD04 for diagnos·
tic tests or in AB02 for normal operation;
bus address overflow is cleared by loading
DRBA; NEX is cleared by loading bit 14
with a zero; ATTN is cleared by user device.
Read only.
14 Nonexistent Memory (NEX) Non-existent memory indicates that as
Unibus master, the DRll-B did not receive
a SSYN 'response 20 usec after asserti ng
MSYN. Cleared by INIT or loading with a 0;
can not be loaded with a 1. Sets ERROR.
Read /Write O.
13 Attention (ATTN) Attention bit that reads the state of the
ATN user signal. Sets ERROR. (Used for
device initiated interrupt.) Set and cleared
by user control only. Read only.
12 Maintenance Maintenance bit used with diagnostic programs.
Cleared by INIT. Read/Write.
11-9 Device Status (DSTAT A.B.C) Device status bits that read the state of
the DSTAT A, B, and C user signals. (Not
tied to interrupt.) Set and cleared by user
control only. Read only.
8 Cycle
CYCLE is used to prime bus cycles; if set
when GO is issued, an immediate bus
cycle occurs. Cleared when bus cycle begins;
cleared by INIT. Read/Write.
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