PDP11 PeripheralsHbk 1972 - Trailing-Edge

Count Set Buffer Register (Write Only)
This is a 16-bit register used for storage of the interval count. It allows automatic
reloading of the COUNTER in MODE 1 operation_ This buffer is set by program
and cleared by program or INIT. (MODE 0 operation clears the buffer on underflow_)
Counter (Address: 772544)
The Counter is a 16-bit, synchronous, binary counter clocked at one of four program-selectable
rates_ It serves in either a cOlfJnt-up or count-down mode_ Underflow
or overflow initiates the interrupt sequence_ The Counter contents may be
read while in operation_ The contents are cleared on clock underflow or overflow
in MODE 0 operation and by INIT_
A third mode utilizes the Counter as an external event counter with the count-up
mode and external count rate enabled.
Priority Level:
Interrupt Vector:
Programmable
Count Rates:
Operating Modes:
BR6 (standard)
104
2 crystal-controlled rates of 100 KHZ and 10 KHZ
1 line frequency
1 external clock input
Single Interrupt
Repeated Interrupt
External Event Counter
No n-I nterru pt
6_2 LINE TIME CLOCK KWll-L
The KWll-L accurately divides time into intervals for more efficient use of PDP-
11 computer time. The intervals are determined by the line frequency, either 50 or
60 Hz. The accuracy of the clock period is that of the frequency source.
6.2.1 Programming
REGISTER
Clock Status Register (LKS)
BIT
15-8
7
6
15 14 13 12 1110 9 8 7
INTERRUPT MONITOR-----------'
INTERRUPT ENABLE-------------'
NAME
Unused
Interrupt Monitor
Interrupt Enable
ADDRESS
777546
6 543 2 1 0
DESCRIPTION
Set when line time clock changes from one
to 0, and clears on a processor DATa to
the LKS when D06 is clear. Set on processor
INIT.
Set on processor DATa to the LKS when
006 is a 1 and cleared on processor DATa
to LKS when D06 is O. Cleared on processor
INIT. When set, enables interrupt.
Monitor goes from 0 to 1. Program may
read or write_ Cleared by INIT.
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