PDP11 PeripheralsHbk 1972 - Trailing-Edge

Signal Name
BUS C
ADRS TO BUS
ADRS TO BUS
DATA TO BUS
DATA TO BUS
END CYCLE
END CYCLE
BUS MSYN
MYSN WAIT
MSYN WAIT
DATA WAIT
DATA WAIT
TIME OUT (1)
TIME OUT (0)
PIN M2
PIN T2
PIN VI
PIN Ul
Table 2-9 M796 Output Signals
Assertion No. of Drive
Level Signals Capability Operation
L
H
L
H
L
H
L
L
H
L
H
L
H
H
H
L
H
L
2
232
UNIBUS
8
10
10
8
10
8
UNIBUS
10
8
10
8
10
10
10
10
10
10
Drives Unibus control
line
Gates BA to address
bus
Gates data to bus
on DATO or DATOB
100 ns-pulse indicating
end of bus
cycle
Drives Unibus
MSYN line
200 ns pulse that delays
assertion of MSYN
Allows for deskewing
of DATA on
DATI. Approximately
200 ns
1 and 0 side of
TIME-OUT Flip-Flop
Output of one-shot
Output of one-shot
Outputs of flip-flop