PDP11 PeripheralsHbk 1972 - Trailing-Edge

Note that in a DATI operation, the DATA WAIT signal is generated when BUS
SSYN is received. The trailing edge of DATA WAIT fires the one-shot that produces
the DATA STROBE signal. This signal gates the data present on the bus data lines
into the device. The trai Ii ng edge of DATA STROBE produces a positive tra nsition
at the DATA ACCEPTED input that results in the clearing of BUS MSYN.
Additional examples of the use of the M796 module are presented in paragraphs
3.5,3.7, and 3.10. The input signals to the module are listed in Table 2-8, and the
output signals are listed in Table 2-9.
Table 2-8 M796 Input Signals
Assertion No. of
Signal Name Level Signals Loading Operation
Cl CONTROL 5 Controls Bus Cl
CO CONTROL 1 Controls Bus CO
PIN H2
PIN HI L 2 1 Produces START
SSYN H 1 2 Negates MSYN on
DATO
DATA ACCEPTED H 2 Negates MSYN on
DATI
INIT H 1 Initializes control
CLEAR TIME OUT L 2 Clears TIME-OUT
Flip-Flop
PIN PI
PIN Rl L 2 Negative edge triggers
one-shot
PIN SI H 2 Positive edge triggers
one-shot
PIN V2 H 2 Clock input to flipflop
PIN U2 L 2 Clears flip-flop
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