PDP11 PeripheralsHbk 1972 - Trailing-Edge

Table 2·6 M795 Output Signals
Assertion No. of Drive
Signal Name Level Signals Capability Operation
BACARRYOUT OV 10 Carry out of low
four bits.
BA OVFL OV 2 10 Register over
WCOVFL flow low level
pulse.
BUS D< 15:00> OV=1 16 UNIBUS Drives data line.
BUS D< 15:00> OV=1 16 UNIBUS Drives address.
2.2.7 M796 UNIBUS Master Control Module
The M796 UNIBUS Master Control Module . provides extremely flexible control
logic that is used to control data transfer operations on the UNIBUS when a device
is functioning as bus master. In addition to controlling the four transfer operations
(DATI, DATIP, DATO, and DATOB), the M796 module generates strobe and
gating signals which transfer both addresses and data to and from the bus; handles
deskewing of data received from the bus; protects against data transfers to
nonexistent devices by the use of time-out circuits; and provides a flip-flop and integrating
one-shot that can be used by the customer for special control functions.
Any device in the PDP-II system may have the capability of gaining control of the
bus and, as bus master, of transferring data to and from other slave devices on
the bus. This operation is performed independently of processor control and is
usually referred to as Direct Memory Access (DMA). The logic neccessary to gain
control of the bus is provided by the M7820 Interrupt Control Module. The M7820
module requests use of the bus (usually by means of an NPR request), receives
the bus grant signal from the processor, asserts selection acknowledge (SACK),
waits until the current bus master releases control of the bus, and then asserts
BUS BUSY, thereby gaining bus control.
Upon becoming bus master, the device is free to conduct a data transfer. A DATI
cycle is performed if the device needs data (either a word or byte) from memory; a
DATa cycle is performed if the device is storing a word of data in memory (DA­
TaB cycle for byte storage); a two-cycle DATIP, DATO(B) operation is performed if
data held in memory is to be modified as in the case of increment memory or add
to memory functions.
In order to execute one of these transfer cycles, the device must set BUS
C< 1:0>for the' required type of data transfer, specify the address of the slave
device partici pating in the transfer, assert the MSYN signa I, a nd then wa it for the
SSYN response from the slave. Data must either be gated to D< 15:00> on a
DATO cycle or be received and strobed at the proper time on a DATI cycle. The
M796 module performs these functions.
Figure 2-20 is a block diagram of the M796 UNIBUS Master control module. The
BUS Cl and BUS CO outputs can directly drive the UNIBUS and are asserted as a
function of the control inputs. Table 2-7 lists the states of the control inputs for
the four possible bus cycles.
226