PDP11 PeripheralsHbk 1972 - Trailing-Edge

5 through 1 of the UNIBUS-to-UNIBUS control status register (UUCSR) in the interface.
The contents of this 5-bit register are used for the five most significant
bits of the secondary bus address. This may be loaded by a MOV BLOCK, UUCSR
instruction.
The interface can be operated in one of two modes. In the first mode, a single bus
operation may access the secondary UNIBUS by addressing the seventhAK field
on the primary UNIBUS. The interface recognizes the address, requests control of
the secondary bus, and interconnects the two sets of bus lines when it receives
control. The interface releases control of the secondary UNIBUS when the transfer
is complete.
In the second mode of operation,if the hold bit is set in the UUCSR, the interface
requests control of the secondary bus and maintains bus mastership until the
hold bit is cleared. This mode of operation permits the primary bus to conduct a
series of data transfers with the secondary bus at the full bus transfer speed. The
only additional time required for a transfer is the signal transmission time within
the interface. The time delays caused by waiting for the secondary bus to grant
bus mastership to the interface are eliminated; therefore, a disk on the primary
bus can transfer data to locations on the secondary bus with the lowest possible
latency delays.
3.8.2 Interface Implementation
In Figure 3-14 UNIBUS 1 (the primary UNIBUS) controls the interface and conducts
data transfers through the interface to UNIBUS 2 (th6 secondary UNIBUS).
The interface control circuit is shown in greater detail in Figure 3-15. This figure
illustrates the UUCSR device register, an address recognition circuit, a MSYN delay
circuit, and several gating circuits. .
When the address asserted on the primary UNIBUS is in the seventh 8K field
(A =00110), the STEAL signal is asserted in the interface. The STEAL L
signal causes an NPR request on the secondary UNIBUS. (If the hold flip-flop is
set, the interface is already bus master and no further bus requests are initiated.)
When the interface becomes a bus master, the MASTER A L signal is asserted.
The combination of STEAL L and MASTER A L produces gating signals to interconnect
the two sets of bus lines as shown in Table 3-1. The MSYN delay circuit
regenerates the 150-ns deskewing period between the assertion of the A and C
lines and the assertion of MSYN on the secondary UNIBUS. This prevents delays
in signal transmission within the interface from affecting the timing on either
UNIBUS_
Table 3-1 Bus Line Gating
Signal From To Gated by: Remarks
A Block Reg UNIBUS2 GATE ADDR ICTRL
A UNIBUS 1 UNIBUS 2 GA TE ADDR ICTRL
C UNIBUS 1 UNIBUS 2 GATE ADDR ICTRL
D UNIBUS2 UNIBUS 1 GATE IN Cl =0 (DATI
or DATIP)
0 UNIBUS 1 UNIBUS 2 GATE OUT Cl = 1 (DATO
or DATOS)
MSYN UNIBUS 1 UNIBUS 2 GATE MSYN
SSYN UNIBUS 2 UNIBUS 1 GATE ADDR ICTRL
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