PDP11 PeripheralsHbk 1972 - Trailing-Edge

2.2.6 M795 Word Count and Bus· Address Module
The M795 Word Count and Bus address Module is used to interface direct
memory access (OMA) devices to the UNIBUS. This module contains two 16·bit
counters: one counter is used to count the number of data transfers that occur;
the other counter is used to specify the bus address of the data to be transferred.
Block transfer devices that function as bus master during data transfers usually
require two registers to hold the parameters of the transfer. One parameter is
transfer count. Initially, a register is loaded with, the 2's complement of the num·
ber of items to be transferred to or from memory. After each transfer is complete,
the register is incremented. If the new value of the register is 0 (indicated by an
overflow), further transfers are inhibited and the block transfer is complete. Since
information can be transferred in words (16 bits each) on the UNIBUS the name
Word Count (WC) is usually assigned to this register. However, the UNIBUS is
also capable of transferring 8·bit bytes of data at a time, and this register may be
used equally as well as a Byte Count register.
The second parameter used in block transfers is the transfer address. Initially, a
register is loaded with an address that specifies the memory location to, or from,
which data is to be transferred. The register is incremented after each transfer;
thus, the register continually "points" to sequential memory locc;ltions. Since
memories and devices have addresses on the UNIBUS, this register is usually
called the Bus address (BA) register.
A simplified block diagram of the M795 module is shown in Figure 2·19. Both the
word count (WC) and bus address (BA) registers consist of 16 flip·flops. These
flip·flop registers can be loaded by placing data on the 16 data line inputs com·
man to both registers and asserting the appropriate loading signal. There are four
independent loading signals: WC high byte, WC low byte, BA high byte, and BA
low byte. Each of the outputs of the 16 bits in the WC register are connected to a
set of DEC 8881 UN IBUS drivers. The contents of the WC register can be gated to
the data bus when the appropriate gate signal is activated. The BA register also
has a set of UN IBUS drivers connected to each output so that the register con·
tents can be gated to the data bus. Note that the driver outputs of both the WC
and BA registers are wire ORd together. In addition, the BA register has a set of
drivers with independent outputs to allow it to drive the address bus.
WC OVFL
LOAD WC
LOAD WC+l
COUNT SA
Figure 2-19 M795 Word Count and Bus Address (block diagram)
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